Xilinx Virtex-II Pro ML324, Руководство пользователя

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12 www.xilinx.com Virtex-II Pro ML324 and ML325 Platform
UG063 (v1.2) May 30, 2006
Detailed Description
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2. Power Supply Jacks
One method of delivering power to the FPGA is by way of the power supply jacks. These
jacks are:
•
AVCCAUX
♦
Supplies power to the RocketIO transceivers on the FPGA
•
VCCAUX
♦
Supplies voltage to the V
AUX
header and the V
AUX
FPGA pins
•
VCCO
♦
Supplies I/O voltages to the FPGA
•
VCORE
♦
Supplies voltage to the core of the FPGA
(Consult the
Virtex-II Pro Platform FPGAs: Complete Data Sheet (DS083) at
http://direct.xilinx.com/bvdocs/publications/ds083.pdf for the maximum
VCORE voltage for the device you are using)
The following two jacks supply termination voltages to the RocketIO transceivers on the
top and bottom edges of the FPGA:
•
VT_TX (top set and bottom set)
•
VT_RX (top set and bottom set)
Note:
5V must always be applied to the 5V jack or to the external power brick connector to power
the 3.3V regulator for the System ACE chip.
3. FPGA Configuration
The FPGA can only be configured in JTAG mode using one of the following options:
•
Parallel Cable III cable
•
Parallel Cable IV cable
•
System ACE configuration controller
(1)
Using the configuration address DIP switches, one of eight bitstreams stored in the
CompactFlash memory can be accessed through the on-board System ACE controller.
Note:
When using the flying wire leads or the Parallel Cable IV cable, the System ACE controller will
be bypassed, thus causing no disruption in the JTAG chain.
1. For further information, consult the System ACE CompactFlash Solution (DS080)
http://www.xilinx.com/bvdocs/publications/ds080.pdf .).