Xilinx Virtex-II Pro ML324, Руководство пользователя

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Virtex-II Pro ML324 and ML325 Platform www.xilinx.com 17
UG063 (v1.2) May 30, 2006
Detailed Description
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10. User Push Buttons (Active High)
There are four active-high push buttons, as shown in Table 12 , connected to user I/O pins
on the FPGA. These push buttons can be used for any purpose that the user sees fit.
11. BERT Headers
There is one pair of 72-position headers intended to be used for parallel Bit Error Rate
Testing (BERT). The odd numbered pins of the BERT headers J56 and J55
are connected to
user I/O pins (see Table 13 , which spans multiple pages). The even numbered pins of J56
and J55 are connected to GND. The third row of header pins (J49) to the left of J55 are
connected to VCCO. This gives the user the ability to jumper I/O pins on J56 to GND and
I/O pins on J55 to either VCCO or GND.
Table 12: User Push Buttons
Label
ML324 ML325
Pin Pin
SW7 D30 G33
SW6 E30 F33
SW3 AL18 D34
SW8 AK18 C34
Table 13: BERT Headers J56 and J55
Header
J56
ML324 ML325
Polarity
Header
J55
ML324 ML325
Polarity
Pin Pin Pin Pin
1 H34 D42 N 1 AB35 AB37 N
2 H33 D41 P 3 AB34 AB36 P
3 H38 E42 N 5 AB37 AD38 N
4 H37 E41 P 7 AB36 AD37 P
5 J39 F42 N 9 AC39 AF40 N
6 J38 F41 P 11 AC38 AF39 P
7 K33 G41 N 13 AD34 AG37 N
8 K34 G42 P 15 AD33 AG38 P
9 K39 J42 N 17 AD38 AK40 N
10 K38 J41 P 19 AD37 AK39 P
11 L37 K41 N 21 AE37 AK36 N
12 L36 K42 P 23 AE36 AK35 P
13 L39 L42 N 25 AE39 AM39 N
14 L38 L41 P 27 AE38 AM38 P
15 M34 N42 N 29 AF34 AP39 N
16 M33 N41 P 31 AF33 AP38 P