Xilinx Virtex-4 ML455, Руководство пользователя

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Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com 45
UG084 (v1.0) May 17, 2005
SelectMAP Clock Selection
R
SelectMAP Clock Selection
There are two clock modes for Slave SelectMAP and one clock mode for Master SelectMAP.
These modes are selected using jumpers with Header P2. The default jumper setting upon
shipment is Master SelectMAP.
Table 4-7 shows the Virtex-4 configuration modes along with the correct settings for the
Mode Switch SW5.
Figure 4-8 shows the clock structure for SelectMAP mode along with Header (P2).
Platform Flash Image Generation and Programming
This section provides general guidelines on how to create a PROM image file with four
different revisions (bitstreams) using the Configuration File Wizard in the iMPACT FPGA
programming tool. Online documentation from the Configuration File Wizard and
iMPACT is available through the
Help -> Help Topics menu selection in iMPACT. Chapter
16 of the Xilinx Development System Reference Guide provides details on how to create a
PROM image file using PROMGen.
Table 4-7: SelectMAP Clock Modes
Mode Function
Header P2 Jumper
Settings
Master SelectMAP
(default) FPGA CCLK drives Flash CLKIN 1-2
Slave SelectMAP 33 MHz oscillator drives FPGA CCLK and
Flash CLKIN 1-2
3-4
Slave SelectMAP 33 MHz oscillator drives Flash CLKIN.
Flash CLKOUT drives FPGA CCLK 1-3
5-6
Figure 4-8: SelectMAP Clock Circuitry
U1 Flash
U10 FPGA
U6 CPLD
P2 Header
U4 33 MHz Oscillator
Master SelectMAP
Slave SelectMAP
Slave SelectMAP
UG084_c4_08_020105
CLKIN
CCLK
1
3
5
2
4
6
CLKOUT
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