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Virtex-4 ML455 PCI/PCI-X Board

www.xilinx.com

UG084 (v1.0) May 17, 2005

SelectMAP Interface

Table 4-3:

Pin Listing for FPGA Configuration Pins

Pin

Number

Net Name

Direction

Pin Type

Description

G14

FPGA_CCLK

I/O

CCLK

Configuration Clock Input or Output

H12

FPGA_RDWR_B

RDWR_B

Active-Low Read Write

G11

FPGA_CS_B

CS_B

Active-Low Chip Select

W15

MODE0

Mode Select 0

Y15

MODE1

Mode Select 1

W15

MODE2

Mode Select 2

H15

PROG_B

PROGRAM_B

Active-Low asynchronous full-chip reset

G15

INIT_B

Active-Low Delay Configuration Pin

H14

FPGA_DONE

DONE

Active-High signal indicating
configuration is complete

Y14

FPGA_BUSY_B

DOUT_BUSY

Active-Low Busy signal

AD13

FLASH_D0

IO_L8N_D0_LC

SelectMAP data bit 0 connected to Flash

AC13

FLASH_D1

IO_L8P_D1_LC

SelectMAP data bit 1 connected to Flash

AC15

FLASH_D2

IO_L7N_D2_LC

SelectMAP data bit 2 connected to Flash

AC16

FLASH_D3

IO_L7P_D3_LC

SelectMAP data bit 3 connected to Flash

AA11

FLASH_D4

IO_L6N_D4_LC

SelectMAP data bit 4 connected to Flash

AA12

FLASH_D5

IO_L6P_D5_LC

SelectMAP data bit 5 connected to Flash

AD14

FLASH_D6

IO_L5N_D6_LC

SelectMAP data bit 6 connected to Flash

AC14

FLASH_D7

IO_L5P_D7_LC

SelectMAP data bit 7 connected to Flash

F13

FORCE

(1, 2)

IO_L1N_D30_LC

Input connected from Pin 31 of CPLD

F12

WIDE

(1, 2)

IO_L2P_D29_LC

Input connected from Pin 29 of CPLD

F11

PCIW_EN

(1, 2)

IO_L2N_D28_LC

Output connected to Pin 33 of CPLD

F16

RTR

(1, 2)

IO_L3P_D27_LC

Output connected to Pin 32 of CPLD

D14

CPLD_SPARE1

(2)

I/O

IO_L4P_D25_LC

Spare I/O connected to CPLD pin 14

D13

CPLD_SPARE2

(2)

I/O

IO_L4N_D24_VREF_LC

Spare I/O connected to CPLD pin 16

D15

CPLD_SPARE3

(2)

I/O

IO_L5P_D23_LC

Spare I/O connected to CPLD pin 18

E14

CPLD_SPARE4

(2)

I/O

IO_L5N_D22_LC

Spare I/O connected to CPLD pin 19

C11

CPLD_SPARE5

(2)

I/O

IO_L6P_D21_LC

Spare I/O connected to CPLD pin 20

D11

CPLD_SPARE6

(2)

I/O

IO_L6N_D20_LC

Spare I/O connected to CPLD pin 21

D16

CPLD_SPARE7

(2)

I/O

IO_L7P_D19_LC

Spare I/O connected to CPLD pin 22

C16

CPLD_SPARE8

(2)

I/O

IO_L7N_D18_LC

Spare I/O connected to CPLD pin 36

E13

CPLD_SPARE9

(2)

I/O

IO_L8P_D17_LC

Spare I/O connected to CPLD pin 37

D12

CPLD_SPARE10

(2)

I/O

IO_L8N_D16_LC

Spare I/O connected to CPLD pin 38

Notes:

1. The Net Names and Directions for pins F13, F12, F11, and F16 were chosen to support a specific PCI/PCI-X design as described

below in

“CPLD Programming Examples.”

The user can use these pins as spare, bidirectional pins.

2. Use LVCMOS_25 I/O standard for general-purpose I/O connected to the CPLD.

www.BDTIC.com/XILINX

Содержание Virtex-4 ML455

Страница 1: ...R Virtex 4 ML455 PCI PCI X Development Kit User Guide UG084 v1 0 May 17 2005 www BDTIC com XILINX...

Страница 2: ...R EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE SPECIFICATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NON...

Страница 3: ...17 Push Button Reset Switch SW7 17 RS232 Port 17 General Purpose I O and LCD Header 19 Power Consumption 20 Voltage Regulators 20 Voltage Regulator Circuit Descriptions 21 LT1764A Voltage Regulators 2...

Страница 4: ...JTAG Port 36 SelectMAP Interface 38 CPLD Programming Examples 43 Static Configuration 43 Generic Dynamic Reconfiguration 44 SelectMAP Clock Selection 45 Platform Flash Image Generation and Programmin...

Страница 5: ...board slot right side The ML455 board is supported by Xilinx PCI and PCI X LogiCORE versions 3 0 and 5 0 respectively Table 1 1 lists the Xilinx PCI and PCI X cores Figure 1 1 Add in Card Connectors T...

Страница 6: ...more information about Xilinx LogiCORE products www xilinx com products design_resources conn_central index htm The following link provides more information about PCI specific applications www xilinx...

Страница 7: ...for up to four FPGA design images in a Xilinx XCF32P FSG48C Platform Flash configuration PROM Static or dynamic device reconfiguration support with the XC2C32 CoolRunner II CPLD 64 bit 3 3V system bo...

Страница 8: ...8 www xilinx com Virtex 4 ML455 PCI PCI X Board UG084 v1 0 May 17 2005 Chapter 1 Introduction R Figure 1 2 shows the ML455 board Figure 1 2 Virtex 4 ML455 Board www BDTIC com XILINX...

Страница 9: ...ML455 board including schematics PCB layout and bill of materials Open the ReadMe txt file on the CD to review the list of contents Initial Board Checks Before Applying Power Perform these steps befor...

Страница 10: ...10 www xilinx com Virtex 4 ML455 PCI PCI X Board UG084 v1 0 May 17 2005 Chapter 2 Getting Started R www BDTIC com XILINX...

Страница 11: ...1 ML455 Board Block Diagram Clock Generator 200 MHz LVPECL Oscillator 133 MHz LVDS Oscillator 33 MHz LVCMOS Oscillator RS 232 DB9M Port P4 General Purpose I O and LCD Header P11 PCI PCI X 64 bit 3 3V...

Страница 12: ...d VCCO PCI_VCC 3 0V P1 PCI Edge Connector I F BANK 8 64 I Os 64 used VCCO 2 5V J4 DDR SODIMM Socket I F BANK 5 64 I Os 64 used VCCO SKT_VCCO 3 0V J1 PCI Socket I F BANK 9 64 I Os 50 used VCCO SKT_VCCO...

Страница 13: ...r P1 pin B16 The clock is then routed in a Y topology to two parallel 0 resistors R2 and R242 The output side of R2 signal PCIBUSCLK1 is routed to FPGA pin C13 the global clock pin of FPGA The output...

Страница 14: ...including device capacity clock speeds and CAS latency options in the 200 pin SODIMM form factor The ML455 board memory interface design includes on board 50 termination resistors to VTT at both the...

Страница 15: ...4 154 DQ47 AB6 41 DQ16 Y26 163 DQ48 AA1 43 DQ17 AB24 165 DQ49 AC4 49 DQ18 AB26 171 DQ50 AB3 53 DQ19 AA26 175 DQ51 AC5 42 DQ20 AE24 164 DQ52 AA8 44 DQ21 AC21 166 DQ53 Y8 50 DQ22 AD19 172 DQ54 AA10 54 D...

Страница 16: ...sts the FPGA pin assignments 139 DQ35 AA3 61 DQS3 Y22 128 DQ36 AC3 133 DQS4 Y1 130 DQ37 AF6 147 DQS5 Y6 136 DQ38 AA7 169 DQS6 AB4 140 DQ39 AA9 183 DQS7 AC1 118 RAS_B AF4 196 SA1 AD8 120 CAS_B AE4 198...

Страница 17: ...Reset Switch SW7 The ML455 board provides a push button switch SW7 for a user assigned function This switch labelled RESET is wired to the CPLD U6 pin 12 general purpose I O pin The switch output is c...

Страница 18: ...X Out Transmit Data TD 3 17 4V RTS Out Request to Send RTS 7 8 4V CTS In Clear to Send CTS 8 9 Up to 25V GND Signal Ground SG 5 9 18 N A Table 3 7 Serial Interface Signal Names and Pin Assignments Sig...

Страница 19: ...tages via the placement of a 0 resistor one only at locations R252 5V or R253 3 3V or R254 SKT_VCCO SKT_VCCO can be either 3 0V or 2 5V selected at the 3 pin header P18 For the LCD mode R243 is remove...

Страница 20: ...grounding PRSNT1 and leaving PRSNT2 open The SKT_PRSNT 1 2 signals on the PCI X expansion socket J1 are routed to the FPGA for sensing A board plugged into the top mounted PCI connector J1 should be c...

Страница 21: ...lator Input U3 PCI 64 bit Socket J1 LED Power D5 D6 VR1 1 25V VTT Regulator None 3 3V N A PCI Edge Connector A10 A16 A21 A27 A33 A39 A45 A53 A59 A66 A75 AB4 B19 B25 B31 B36 B91 B93 B54 B59 B70 B79 B88...

Страница 22: ...U3 and U4 Figure 3 5 LT1764A Voltage Regulator Circuit Table 3 10 LT1764 Resistor Calculations VOUT R1 R2 VCALC Calc Diff Diff U2 2 50V 5 2 375 169 162 2 370367657 0 051852937 5 2 Nom 2 500 169 182 2...

Страница 23: ...en plugged back into the original formula gives VOUT 1 8137244V 0 762 difference PCI 3 0V Interface Voltage Regulator Figure 3 7 shows the LT1764AEQ U3 voltage regulator set at 3 0V This regulator sou...

Страница 24: ...K 1 resistors in series is applied to the U2 2 5V output to create the 1 25V reference module input voltage The module output closely tracks the input The data sheet for the TI module is located at h...

Страница 25: ...29 A22 EDGE_AD28 B22 GND A23 EDGE_AD26 B23 EDGE_AD27 A24 GND B24 EDGE_AD25 A25 EDGE_AD24 B25 VCC3V3 A26 EDGE_IDSEL B26 EDGE_CBE3 A27 VCC3V3 B27 EDGE_AD23 A28 EDGE_AD22 B28 GND A29 EDGE_AD20 B29 EDGE_A...

Страница 26: ...E_AD8 A53 VCC3V3 B53 EDGE_AD7 A54 EDGE_AD6 B54 VCC3V3 A55 EDGE_AD4 B55 EDGE_AD5 A56 GND B56 EDGE_AD3 A57 EDGE_AD2 B57 GND A58 EDGE_AD0 B58 EDGE_AD1 A59 VCC3V3 B59 VCC3V3 A60 EDGE_REQ64_B B60 EDGE_ACK6...

Страница 27: ...PCI X LogiCORE intellectual property cores available to facilitate getting started with application specific design A72 GND B72 EDGE_AD57 A73 EDGE_AD56 B73 GND A74 EDGE_AD54 B74 EDGE_AD55 A75 VCC3V3 B...

Страница 28: ...66 MHz operation M66EN is pulled up on the system board PME Power Management Event P1 A19 is wired to a two pin header pin P7 1 PME is pulled up on the system board P7 2 is wired to U10 LX25 Bank 6 pi...

Страница 29: ...B5 VCC5 A6 SKT_INTA_I_B B6 VCC5 A7 SKT_INTC_I_B B7 SKT_INTB_I_B A8 VCC5 B8 SKT_INTD_I_B A9 unused B9 SKT_PRSNT1_B A10 VCC3V3 B10 unused A11 unused B11 SKT_PRSNT2_B 3 3V KEY 3 3V KEY 3 3V KEY 3 3V KEY...

Страница 30: ...T_SMBCLK B40 SKT_PERR_B A41 SKT_SMBDAT B41 VCC3V3 A42 GND B42 SKT_SERR_B A43 SKT_PAR B43 VCC3V3 A44 SKT_AD15 B44 SKT_CBE1_B A45 VCC3V3 B45 SKT_AD14 A46 SKT_AD13 B46 GND A47 SKT_AD11 B47 SKT_AD12 A48 G...

Страница 31: ...71 SKT_AD59 A72 GND B72 SKT_AD57 A73 SKT_AD56 B73 GND A74 SKT_AD54 B74 SKT_AD55 A75 VCC3V3 B75 SKT_AD53 A76 SKT_AD52 B76 GND A77 SKT_AD50 B77 SKT_AD51 A78 GND B78 SKT_AD49 A79 SKT_AD48 B79 VCC3V3 A80...

Страница 32: ...tion device U10 XC4VLX25 FPGA Bank 1 U10 XC4VLX25 FPGA Bank 0 Configuration I F P3 Configuration Image select header SW6 PROG SW7 General purpose push button switches All XC2C32 I O are 2 5V and the X...

Страница 33: ...0 pdf UG071 Virtex 4 Configuration Guide http www xilinx com bvdocs userguides ug071 pdf PCI Special Interest Group PCISIG PCI and PCI X specifications are available from the PCI Special Interest Grou...

Страница 34: ...34 www xilinx com Virtex 4 ML455 PCI PCI X Board UG084 v1 0 May 17 2005 Chapter 3 Hardware Description R www BDTIC com XILINX...

Страница 35: ...bitstreams for programming the FPGA The unique combination of the FPGA connected to the Platform Flash through the CPLD allows for static and dynamic bitstream selection of the FPGA via Slave and Mas...

Страница 36: ...provides a JTAG connector P5 to configure the Virtex 4 FPGA and program JTAG devices located in the JTAG chain Figure 4 3 shows the pin assignments for the JTAG connector The JTAG cable connects to P5...

Страница 37: ...escriptions and Pin Assignments Signal Name Description P5 Pin Number FPGA Pin Number CPLD Pin Number Flash Pin Number JTAG_TMS JTAG TMS to FPGA CPLD FLASH 4 Y11 10 E2 JTAG_TCK JTAG TCK to FPGA CPLD F...

Страница 38: ...able 4 5 list the pinouts for the FPGA CPLD and Platform Flash respectively Figure 4 5 Schematic of Flash CPLD FPGA SelectMAP Interface D 0 7 REV_SEL0 REV_SEL1 CLKOUT To P2 From P2 CLKIN U1 Platform F...

Страница 39: ...C14 FLASH_D7 I IO_L5P_D7_LC SelectMAP data bit 7 connected to Flash F13 FORCE 1 2 I IO_L1N_D30_LC Input connected from Pin 31 of CPLD F12 WIDE 1 2 I IO_L2P_D29_LC Input connected from Pin 29 of CPLD F...

Страница 40: ...UT Busy pin from FPGA 23 FPGA_CS_B I IO14 Chip Select from FPGA 5 FPGA_DONE I IO3 DONE pin from FPGA 34 FPGA_RDWR_B O IO GOE4 Output connected to RDWR_B pin of FPGA 27 INIT_B O IO15 Output connected t...

Страница 41: ...mber Net Name Direction Pin Type Description Table 4 5 Pin Listing for Flash Pin Number Net Name Direction Pin Type Description C1 BUSY_TO_FLASH_B I BUSY Active Low Busy signal connected from CPLD Pin...

Страница 42: ...ound F6 GND I GND6 Ground H1 GND I GND7 Ground B1 VCC1V8 I VCCINT1 1 8V Power E1 VCC1V8 I VCCINT2 1 8V Power G6 VCC1V8 I VCCINT3 1 8V Power H2 VCC1V8 I VCCJ 1 8V Power D6 VCC2V5 I VCCO3 2 5V I O Power...

Страница 43: ...nfiguration for Static Configuration D 0 7 REV_SEL0 REV_SEL1 CLKOUT To P2 From P2 CLKIN CF OE RESET D 7 0 CCLK M0 M1 M2 CPLD_SPARE 1 10 FORCE 1 WIDE 1 PCIW_EN 1 RTR 1 DONE DOUT_BUSY RDWR_B CS_B PROG_B...

Страница 44: ...verride the dynamic reconfiguration and allow only static configuration as described in XAPP693 A CPLD Based Configuration and Revision Manager from Xilinx Platform Flash PROMs and FPGAs This applicat...

Страница 45: ...sions bitstreams using the Configuration File Wizard in the iMPACT FPGA programming tool Online documentation from the Configuration File Wizard and iMPACT is available through the Help Help Topics me...

Страница 46: ...xt 3 Under Prepare Configuration Files select PROM File then click Next 4 Under Prepare PROM Files shown in Figure 4 9 select the following Select the Xilinx PROM with Design Revisioning Enabled radio...

Страница 47: ...for the bitfile you want for Configuration Address 0 and click Open 4 Under Add Device Would you like to add to Revision 0 click No 5 Browse for the bitfile you want for Configuration Address 1 and c...

Страница 48: ...Scan the JTAG chain by clicking the scan chain icon 3 The Boundary Scan Summary indicates four devices are found Click OK 4 Under Assign New Configuration File click Cancel All 5 Double click on the t...

Страница 49: ...Virtex 4 ML455 PCI PCI X Board www xilinx com 49 UG084 v1 0 May 17 2005 Platform Flash Image Generation and Programming R Figure 4 11 Programming the PROM UG084_c4_11_022705 www BDTIC com XILINX...

Страница 50: ...50 www xilinx com Virtex 4 ML455 PCI PCI X Board UG084 v1 0 May 17 2005 Chapter 4 Configuration R www BDTIC com XILINX...

Страница 51: ...for the mother board s clock net characteristics The differences between the six simulations are based on the top and bottom jumpers Figure A 1 Bottom Jumper in Place R242 only Figure A 2 Top Jumper i...

Страница 52: ...igure A 3 Both Jumpers in Place R2 and R242 UG084_apx_02_051105 Voltage mV Time ns 500 0 0 000 500 0 1000 0 1500 0 2000 0 2500 0 3000 0 3500 0 4000 0 4500 0 0 000 5 000 10 000 15 000 20 000 25 000 30...

Страница 53: ...a Transmission Line Hard Routed through the Net UG084_apx_04_051105 Voltage mV Time ns 500 0 0 000 500 0 1000 0 1500 0 2000 0 2500 0 3000 0 3500 0 4000 0 4500 0 0 000 5 000 10 000 15 000 20 000 25 00...

Страница 54: ...ther destination pin U10 C13 or U10 D2 Figure A 6 Top and Bottom Jumpers are Transmission Lines Hard Routed through Nets UG084_apx_06_051105 Voltage mV Time ns 500 0 0 000 500 0 1000 0 1500 0 2000 0 2...

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