Video Input/Output Daughter Card
45
UG235 (v1.2.1) October 31, 2007
PicoBlaze Controller for the ADV7321B Video Encoder
R
In HD-SDI mode, there are two possible bit rates, 1.485 Gb/s and 1.4835 Gb/s. These
require 74.25 MHz and 74.1758 MHz reference clock frequencies, respectively. The
ICS664-02 frequency synthesizer can produce both of these frequencies. The RocketIO
receiver uses this reference clock to “spin up” its clock and data recovery system. After
locked to the bitstream, the RocketIO receiver produces a recovered clock on its
RXRECCLK output port, running at the word rate of the recovered video data (either
74.25 MHz or 74.1578 MHz). Twenty bits of recovered data will be output on the RXDATA
port every cycle of RXRECCLK.
RXRECCLK, the recovered clock produced by the RocketIO receiver, is buffered by a
global clock buffer and used to clock the HD-SDI receiver logic in the FPGA. The data first
passes through a descrambler to remove the NRZI encoding and scrambling. Next, the
data is aligned to word boundaries by a framer. The output of the framer is two 10-bit
ports, one for the luma (Y) channel information and the other the chroma (C) channel
information. These two channels are checked for CRC errors and then output to the
ADV7321B video encoder device to be converted to HD analog component video. Note
that the HD-SDI receiver is capable of receiving some HD video formats not supported by
the ADV7321B. In these cases, the ADV7321B’s outputs are blanked.
The receiver works somewhat differently in SD-SDI mode. The 270 Mb/s bit rate of SD-
SDI is below the minimum bit rates supported by the RocketIO receiver. For SD-SDI, the
RocketIO receiver is used as an asynchronous oversampler and data recovery is not done
in the RocketIO itself. The RocketIO receiver is given a 108 MHz reference clock. This is
multiplied by 20 in the RocketIO receiver causing it to sample the bitstream at a 2.16 GHz
rate, eight times faster than the 270 Mb/s bit rate. The RXRECCLK output clock from the
RocketIO receiver is equal in frequency to the reference clock (108 MHz) and is not a true
recovered clock. The RocketIO receiver outputs 20 bits of 8X oversampled data every cycle
of RXRECCLK.
The oversampled data from the RocketIO receiver goes into a data recovery unit. This unit
examines the oversampled data and recovers the actual data from the bitstream. It outputs
the recovered data as 10-bit data words. Whenever the data recovery unit has 10-bits of
recovered data ready, it asserts a data ready signal. This data ready signal is used as a clock
enable to the receiver logic downstream from the data recovery unit. This clock enable
signal is synchronous with the 108 MHz RXRECCLK from the RocketIO receiver. It is
asserted, on average, one out of every four cycles of RXRECCLK to give an effective data
rate of 27 MHz.
The recovered data passes through a SD-SDI descrambler and then a framer. The output of
the framer is word aligned in the recovered video stream. The Y and C components of the
video stream alternate every clock cycle on the output of the framer. The video stream is
checked for errors by an EDH processor. Errors can only be detected if the incoming video
has embedded EDH packets compliant with SMPTE RP 165. Finally, the video is sent to the
ADV7321B video encoder and output from the VIODC as analog composite video. The
data ready signal from the data recovery unit, used as a clock enable to the SDI receiver
logic, is output to the ADV7321B encoder as a 27 MHz video clock for the SD video.
PicoBlaze Controller for the ADV7321B Video Encoder
A PicoBlaze soft processor in the Virtex-II Pro FPGA is used to setup and control the
ADV7321B video encoder. The PicoBlaze controls the ADV7321B through the I
2
C interface.
The PicoBlaze processor monitors the SDI receiver status and whenever the receiver
changes between HD and SD or whenever the video format being received changes, the
PicoBlaze makes appropriate changes to the configuration of the ADV7321B encoder
through the I
2
C interface.
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