Video Input/Output Daughter Card
37
UG235 (v1.2.1) October 31, 2007
Bus Interface
R
(black arrows). It is also important to note that the VCO frequency range and charge pump
currents must be configured to match the expected frequency.
Setting the feedback divider correctly results in the correct sample frequency, but the
sample phase must also be set. Under ideal conditions, the phase delay would be T/2, to
sample at the center of the pixels. This makes T/2 a reasonable default value. Under actual
operating conditions, there can be skew between the HSYNC signal and the video data
thus requiring phase adjustment.
The process above is quite straightforward if one knows the proper settings for a given
source. VESA timing standards are a good place to start for standard resolutions.
Unfortunately, graphics adapters often do not follow these exactly. In this case, the PLL
divider value and phase must be adjusted to properly digitize the source. This process is
beyond the scope of this document.
Setting Black Levels
The primary mechanism for setting the black level is the input clamp. This clamps the
input to ground, resulting in a DC offset in the coupling capacitor (just outside the
AD9887A) equal to the difference between the current input voltage and ground. After the
clamp is released, this difference is effectively subtracted from the raw input signal,
resulting in an input signal reference to ground. For this circuit to function properly, this
clamp should only be enabled when the input data is known to be black, such as during the
horizontal back porch. The AD9887A has a clamp placement register to control the start of
the clamp, in cycles after the falling edge of HSYNC. The clamp duration register controls
the length of the clamp, in cycles.
The AD9887A also includes offset registers to offset the black level of each color
individually. This control is typically not needed.
Setting Gain
The AD9887A includes gain registers to adjust the input range of the ADC. Setting this too
low results in a dim display, while setting it too high results in saturation and clipping of
brighter colors.
Bus Interface
The AD9887A data output is synchronous to a differential clock, DATACK. The pixel data
is 8 bits per color. There are two pixel buses, A and B. There are also three key sync signals
– HS, VS, and DE.
The data bus can be operated in either single pixel mode or dual pixel mode. Single pixel
mode only uses port A and the clock rate is equal to the pixel rate. In dual pixel mode, port
A carries even pixels and port B carries odd pixels, and the clock rate is half the pixel rate.
The single pixel more would be desirable to reduce the number of signals, but the
AD9887A has a max DATACK frequency of 140 MHz, so for pixel rates greater than
140 MHz, the bus has to be operated in dual pixel mode.
Figure 4-5:
Ideal ADC Sampling Positions
HSYNC
RGB
0
1
2
3
4
5
6
7
8
9
10
11
10
11
0
Sample
www.BDTIC.com/XILINX
