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Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
Chapter 9:
Analog Capture Circuit
R
Digital Outputs from Analog Inputs
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by
Equation 9-1
.
Equation 9-1
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in
Table 9-2
.
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
divider shown in
Figure 9-2
. Consequently, 1.65V is subtracted from the input voltage on
VINA or VINB.
The maximum range of the ADC is
±
1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
Figure 9-2:
Detailed View of Analog Capture Circuit
Header J22
SPI_MOSI
AMP_CS
SPI_SCK
AMP_SHDN
AMP_DOUT
(D16)
(AB14)
(AA20)
(W15)
(W6)
FPGA
LTC 6912-1 AMP
DAC_REF_AB
DAC_REF_CD
VINA
VINB
GND
VCC
(3.3V)
(3.3V)
(3.3V)
REF = 1.65V
A
B
CS/LD
DIN
SCK
SHDN
DOUT
SPI Control Interface
A GAIN
B GAIN
SCK
CONV
SDO
SPI Control Interface
CHANNEL 1 CHANNEL 0
AD_CONV
(Y6)
AD_DOUT
(T7)
14
14
LTC 1407A-1 ADC
A/D
Channel 0
A/D
Channel 1
3
2
1
0
3
2
1
0
13
0
...
13
0
...
UG334_c9_02_052407
DAC_REF_CD reference voltage is nominally 3.3V.
The reference is supplied by the LP3906 adjustable regulator, IC18.
The voltage is adjustable using the regulator’s I C interface.
2
D
13:0
[
]
GAIN
V
IN
1.65
V
–
(
)
1.25
V
------------------------------------
×
8192
×
=
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