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Spartan-3A/3AN FPGA Starter Kit Board User Guide
UG334 (v1.1) June 19, 2008
Chapter 5:
Character LCD Screen
R
After the write operation, the address is automatically incremented or decremented by 1
according to the
Entry Mode Set
command. The entry mode also determines display shift.
Execution Time: 40
µ
s
Read Data from CG RAM or DD RAM
Reads data from DD RAM if the command follows a previous
Set DD RAM Address
command, or reads data from CG RAM if the command follows a previous
Set CG RAM
Address
command.
After the read operation, the address is automatically incremented or decremented by 1
according to the
Entry Mode Set
command. However, a display shift is not executed
during read operations.
Execution Time: 40
µ
s
Operation
The board has an eight-bit data interface to the character LCD. Other Xilinx boards use a
four-bit interface. As shown in
Figure 5-1
, the Spartan-3A/3AN Starter Kit board supports
both an eight-bit and a four-bit interface for compatibility reasons. Many existing reference
designs are already built around a four-bit interface.
Four-Bit Data Interface
Figure 5-6
illustrates a write operation to the LCD, showing the minimum times allowed
for setup, hold, and enable pulse length relative to the 50 MHz clock (20 ns period)
provided on the board.
Содержание Spartan-3A DSP FPGA Series
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