Kintex UltraScale KCU1500 Acceleration Development Board
21
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 3:
Hardware Platform
• The
M00_AXI
through
M03_AXI
interfaces are high-bandwidth, 512-bit AXI
memory-mapped master interfaces that indirectly connect to the four DDR4 IP memory
controller instances as previously described in
Chapter 2, Platform Characteristics
,
sections
Sparse Memory Connectivity
and
Stacked Silicon Interconnect (SSI)
Technology Support
.
• The
CONTROL_CLK
and
CONTROL_RESET
ports are clock and reset synchronous to the
slower
S_AXI
(AXI4-Lite control) interface.
• The
DATA_CLK
and
DATA_RESET
ports are clock and reset for the primary data paths
used in the kernel(s) as well as the
M00_AXI
through
M03_AXI
interfaces.
• The
KERNEL_CLK2
and
KERNEL_RESET2
ports are clock and reset for an optional
second domain which can be used only in RTL user kernels. As needed, this domain
provides users the flexibility to run logic in RTL kernels at a different frequency than, or
generally asynchronous to, the
DATA_CLK
and
DATA_RESET
domain.
IMPORTANT:
Data paths must be synchronous to the DATA_CLK and DATA_RESET domain on the
output interfaces of the kernel(s), making the RTL kernel developer responsible for transferring data
from the KERNEL_CLK2 domain into the DATA_CLK domain on egress of the kernel.
The SDAccel OpenCL Programmable Region IP core is a hierarchical IP. Viewing its contents
reveals the subsystem block diagram shown in the following figure.
• The four “add one” training kernel instances,
kernel_0
through
kernel_3
, are
connected to the single
S_AXI
slave control interface of the Programmable Region
using a 1x4 AXI Interconnect instance, which also performs domain crossing between
CONTROL_CLK
and
CONTROL_RESET
on its slave interface (Programmable Region
boundary-facing) side, and
DATA_CLK
and
DATA_RESET
on its master interface
(kernel-facing) side.
X-Ref Target - Figure 3-9
Figure 3-9:
SDAccel OpenCL Programmable Region Hierarchical IP Subsystem
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