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KCU1250 IBERT Getting Started Guide

27

UG1061 (v2017.4) December 20, 2017

www.xilinx.com

Chapter 2:

Creating the GTH IBERT Core

4. Back on the

Manage IP

window, select

Verilog

for Target language,

Vivado Simulator

for Target simulator,

Mixed

for Simulator language, and a directory to save the

customized IP (

Figure 2-3

). Click

Finish

.

Note:

Make sure the directory name does not include spaces.

X-Ref Target - Figure 2-3

Figure 2-3:

Manage IP Settings

;

Send Feedback

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Содержание Kintex UltraScale FPGA KCU1250

Страница 1: ...Kintex UltraScale FPGA KCU1250 Characterization Kit IBERT Getting Started Guide Vivado Design Suite UG1061 v2017 4 December 20 2017...

Страница 2: ...Figure 1 14 Figure 2 1 Figure 2 2 and Figure 2 4 06 08 2016 2016 2 Updated for Vivado Design Suite 2016 2 Design file changed to rdf0352 kcu1250 ibert 2016 2 zip Updated Figure 2 11 Figure 2 12 and Fi...

Страница 3: ...4 Requirements 5 Setting Up the KCU1250 Board 5 Extracting the Project Files 6 Running the GTH IBERT Demonstration 7 Chapter 2 Creating the GTH IBERT Core Appendix A Warranty Appendix B Additional Re...

Страница 4: ...cure Digital SD memory card provided with the KCU1250 board The demonstration shows the capabilities of the Kintex UltraScale XCKU040 FFVA1156 FPGA GTH transceiver The KCU1250 board is described in de...

Страница 5: ...odule installed SuperClock 2 module Rev 1 0 installed Active BGA heat sink installed 12V DC power adapter Two USB cables standard A plug to micro B plug Host PC with SD card reader USB ports Xilinx Vi...

Страница 6: ...KCU1250 board b Using three 4 40 x 0 25 inch screws firmly screw down the module from the bottom of the KCU1250 board c On the SuperClock 2 module place a jumper across pins 2 3 2V5 of the CONTROL VOL...

Страница 7: ...can be tested by following a similar series of steps Connecting the GTH Transceivers and Reference Clocks Figure 1 1 shows the locations for GTH transceiver Quads 224 225 226 227 and 228 on the KCU125...

Страница 8: ...ions of the differential clock SMA connectors on the clock module which can be connected to the reference clock cables The four SMA pairs labeled CLKOUT provide LVDS clock outputs from the Si5368 cloc...

Страница 9: ...sembly to the bottom of the connector housing if it is not already inserted see Figure 1 4 Note Figure 1 4 is for reference only and might not reflect the current version of the connector 2 Attach the...

Страница 10: ...ck CLKOUT1_P and CLKOUT1_N are used here as an example GTH TX RX Loopback Connections 1 See Figure 1 2 to identify the P and N coax cables that are connected to the four receivers RX0 RX1 RX2 and RX3...

Страница 11: ...Getting Started Guide Figure 1 8 shows the KCU1250 board with the cable connections required for the Quad 224 GTH IBERT demonstration X Ref Target Figure 1 7 Figure 1 7 TX to RX Loopback Connection Ex...

Страница 12: ...hich can be accessed through a serial communication terminal connection using the enhanced communication port of the Silicon Labs USB to Dual UART Bridge Figure 1 9 Additional information about the Si...

Страница 13: ...using one of the standard A plug to micro B plug USB cables provided Figure 1 11 4 Power up the board by placing SW1 in the ON position 5 Open a serial communication terminal application on the host c...

Страница 14: ...es a System Integrated Configuration Engine System ICE option The System ICE can be used to configure the FPGA in 8 bit SMAP configuration mode using one of the bit files provided on the SD card The F...

Страница 15: ...with the Quad 224 IBERT example design Press Enter and review the terminal for configuration progress Enter a Bitstream number 0 15 0 Info xilinx sys opened Info Opening rev_1 set0 config def Info Con...

Страница 16: ...Suite 1 Connect the host computer to the KCU1250 board using the second standard A plug to micro B plug USB cable The standard A plug connects to a USB port on the host computer and the micro B plug...

Страница 17: ...www xilinx com Chapter 1 KCU1250 IBERT Getting Started Guide 2 Start the Vivado Design Suite on the host computer and click Flow Open Hardware Manager highlighted in Figure 1 14 X Ref Target Figure 1...

Страница 18: ...apter 1 KCU1250 IBERT Getting Started Guide 3 In the Hardware Manager window Figure 1 15 click Open New Target 4 In the Hardware Server Settings window select Local server target is on local machine C...

Страница 19: ...ncy at the default value 15 MHz Click Next 6 In the Open Hardware Target Summary window click Finish The wizard closes and the Vivado Design Suite opens the hardware target To view the GTH transceiver...

Страница 20: ...IBERT Getting Started Guide 20 UG1061 v2017 4 December 20 2017 www xilinx com Chapter 1 KCU1250 IBERT Getting Started Guide X Ref Target Figure 1 17 Figure 1 17 Serial I O Analyzer Create Links Send F...

Страница 21: ...eate links select the TX GT and RX GT from the two lists then click the Add button For this project connect the following links Figure 1 18 MGT_X0Y0 TX xcku040_0 Quad_224 to MGT_X0Y0 RX xcku040_0 Quad...

Страница 22: ...ure 1 19 Verify that the there are no bit errors In Case of RX Bit Errors If there are initial bit errors after linking or as a result of changing the TX or RX pattern click the respective BERT Reset...

Страница 23: ...itional information on the Vivado Design Suite and IBERT core can be found in Vivado Design Suite User Guide Programming and Debugging UG908 Ref 5 Closing the IBERT Demonstration To close the IBERT de...

Страница 24: ...ad GTH IBERT core The procedure assumes Quad 224 at 12 5 Gb s line rate but cores for any of the GTH Quads with any supported line rate can be created following the same series of steps For more detai...

Страница 25: ...250 IBERT Getting Started Guide 25 UG1061 v2017 4 December 20 2017 www xilinx com Chapter 2 Creating the GTH IBERT Core X Ref Target Figure 2 1 Figure 2 1 Vivado Design Suite Initial Window Send Feedb...

Страница 26: ...ing the GTH IBERT Core 3 In the Manage IP Settings window click the button next to the Part field to select the target part Use the drop down menu items to filter the devices Select the xcku040 ffva11...

Страница 27: ...4 Back on the Manage IP window select Verilog for Target language Vivado Simulator for Target simulator Mixed for Simulator language and a directory to save the customized IP Figure 2 3 Click Finish N...

Страница 28: ...er 20 2017 www xilinx com Chapter 2 Creating the GTH IBERT Core 5 In the IP Catalog window expand the Debug Verification folder expand the Debug folder and double click IBERT UltraScale GTH Figure 2 4...

Страница 29: ...m Chapter 2 Creating the GTH IBERT Core 6 A Customize IP window opens In the Protocol Definition tab set the LineRate Gb s to 12 5 Gbps Change Refclk MHz to 125 Keep defaults for other fields Figure 2...

Страница 30: ...Creating the GTH IBERT Core 7 In the Protocol Selection tab use the Protocol Selected drop down menu next to QUAD_224 to select Custom 1 12 5 Gb s and select MGTREFCLK0 224 from the REFCLK Selection m...

Страница 31: ...TH IBERT Core 8 In the Clock Settings tab select DIFF SSTL15 for the I O Standard enter E18 for the P Package Pin the FPGA pins to which the system clock is connected and make sure the Frequency MHz i...

Страница 32: ...Core 9 From the Project Manager window in the Sources window right click the IBERT IP and select Open IP Example Design Figure 2 8 Specify a location to save the design click OK and the example desig...

Страница 33: ...2017 4 December 20 2017 www xilinx com Chapter 2 Creating the GTH IBERT Core 10 In the Sources window Design Sources should now show the IBERT design example Figure 2 9 X Ref Target Figure 2 9 Figure...

Страница 34: ...34 UG1061 v2017 4 December 20 2017 www xilinx com Chapter 2 Creating the GTH IBERT Core 11 Click Run Synthesis from the Flow Navigator to synthesize the design Figure 2 10 X Ref Target Figure 2 10 Fig...

Страница 35: ...one a Synthesis Completed window opens Select Run Implementation and click OK Figure 2 11 13 When the implementation is done an Implementation Completed window opens Select Generate Bitstream and clic...

Страница 36: ...RT Core 14 When the Bitstream Generation Completed dialog window appears click Cancel Figure 2 13 15 Navigate to the ibert_ultrascale_gth_0_example ibert_ultrascale_gth_0_example runs impl_1 directory...

Страница 37: ...glect or default of Customer For any breach by Xilinx of this limited warranty the exclusive remedy of Customer and the sole liability of Xilinx shall be at the option of Xilinx to replace or repair t...

Страница 38: ...ilinx documents videos and support resources which you can filter and search to find information To open the Xilinx Documentation Navigator DocNav From the Vivado IDE select Help Documentation and Tut...

Страница 39: ...hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xil...

Страница 40: ...UTOMOTIVE SAFETY STANDARD SAFETY DESIGN CUSTOMER SHALL PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES USE OF PRODUCTS IN A SAFETY...

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