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ChipScope Pro Software and Cores User Guide

UG029 (v14.3) October 16, 2012

Chapter 5:

ChipScope Engine Tcl Interface

::chipscope::csejtag_tap set_irlength

This subcommand sets the instruction register (IR) length of a single device in the current
JTAG chain. The

length is used to determine the amount of padding required to shift an

instruction into a device register. TAP shift and navigate operations do not work until all
devices have the IR lengths set up correctly. The

::chipscope::csejtag_tap

autodetect_chain

subcommand automatically sets up IR lengths for all devices in the

chain that support the

IDCODE

command.

Note:

The JTAG target must be locked by using the

::chipscope::csejtag_target lock

subcommand before calling this subcommand. Also, the device count must be set prior to calling this
subcommand using the

::chipscope::csejtag_tap set_device_count

Syntax

::chipscope::csejtag_tap set_irlength handle deviceIndex irLength

Arguments

Returns

An exception is thrown if the subcommand fails.

Example

Set the IR length of the device at index 0 to 11 bits.

%::chipscope::csejtag_tap set_irlength $handle 0 11

Back to list of all CseJtag Tcl Commands

Table 5-32:

Arguments for Subcommand ::chipscope::csejtag_tap set_irlength

Argument

Type

Description

handle

Required

Handle to the session that is returned by

::chipscope::csejtag_session create

deviceIndex

Device index (0 to

-1) in the

-length JTAG chain.

irLength

Length of the IR (in bits)

Содержание ChipScope Pro

Страница 1: ...following software versions ISE Design Suite 14 3 through 14 6 This document applies to the following software versions ISE Design Suite 14 3 through 14 6 This document applies to the following softw...

Страница 2: ...ion to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials...

Страница 3: ...pe Pro Core Inserter with ISE Project Navigator 33 Using the ChipScope Pro Core Inserter with Command Line Implementation 35 ChipScope Pro Core Inserter Features 38 Chapter 4 Using the ChipScope Pro A...

Страница 4: ...pe Pro Software and Cores User Guide www xilinx com 4 UG029 v14 3 October 16 2012 ChipScope Pro Analyzer Core Troubleshooting 217 Gathering Information for Xilinx Technical Support 223 Appendix B Refe...

Страница 5: ...lled MGTs multi gigabit transceivers The IBERT core supports the high speed serial transceivers found in the Xilinx Virtex 7 Kintex 7 Virtex 6 Spartan 6 and Virtex 5 FPGA devices listed in the ISE Des...

Страница 6: ...formation on this feature go to PlanAhead Design Analysis Tool See Reference 17 p 225 ChipScope Pro Analyzer Tool Provides in system device configuration as well as trigger setup trace display control...

Страница 7: ...ate trigger ports each with a user selectable width of 1 to 256 channels for a total of up to 4096 trigger channels Multiple separate trigger ports increase the flexibility of event detection and redu...

Страница 8: ...esign for greater accuracy Multiple trigger settings Records duration and number of events along with matches and ranges for greater accuracy and flexibility Downloadable from the Xilinx Web site Tool...

Страница 9: ...at the HDL signals you want to debug could be optimized away or obfuscated during synthesis process Most signals that are interesting for debug such as outputs of registers block RAM etc are not adver...

Страница 10: ...ignal of your design Because the ILA core is synchronous to the design being monitored all design clock constraints that are applied to your design are also applied to the components inside the ILA co...

Страница 11: ...ges Performs and comparisons Detects high to low and low to high bit wise transitions Compares up to 4 bits per slice in LUT4 based devices Compares up to 8 bits per slice in LUT6 based devices Extend...

Страница 12: ...ger Output Port The internal trigger condition of the ILA core can be accessed using the optional trigger output port This signal can be used as a trigger for external test equipment by attaching the...

Страница 13: ...you would not be able to monitor for individual bit transitions on the CE WE and OE signals while looking for the Address bus to be in a specified range The flexibility of being able to choose from di...

Страница 14: ...sure that both the TRIG0 and TRIG1 trigger ports each have two match units attached to them one for the trigger condition and one for the storage qualification condition Here is how you would set up t...

Страница 15: ...le buffer are filled or until you halt the ILA core N Samples Capture Mode The N Samples capture mode is similar to the Window capture mode except for two major differences The number of samples per w...

Страница 16: ...tputs You define these in the ChipScope Pro Analyzer tool They are synchronized to the design clock and driven out of the core to the surrounding design A logical 1 or 0 can be defined for individual...

Страница 17: ...output slew rate on each output data pin on an individual pin by pin basis Supports any Agilent probe connection technology See Reference 25 p 226 The maximum number of data probe points available at...

Страница 18: ...re specified options are chosen and the Generator runs the entire implementation flow including bitstream creation in one step The design flow for generating IBERT core designs for Virtex 7 Kintex 7 V...

Страница 19: ...change line rates at generate time Ability to set reference clock sources at generate time Limited PCS support including loopback Pattern encoding clock correction and channel bonding are not support...

Страница 20: ...le can be either 32 or 40 bits wide and selectable at generate time BERT Parameters Number of bits received in error and total number of words received are gathered dynamically and read out by the Chi...

Страница 21: ...ble at generate time BERT Parameters Number of bits received in error and total number of words received are gathered dynamically and read out by the ChipScope Pro Analyzer tool Polarity The polarity...

Страница 22: ...wide and selectable at generate time BERT Parameters Number of bits received in error and total number of words received are gathered dynamically and read out by the ChipScope Pro Analyzer tool Polari...

Страница 23: ...bits BERT Parameters Number of bits received in error and total number of words received are gathered dynamically and read out by the ChipScope Pro Analyzer tool Polarity The polarity of the TX or RX...

Страница 24: ...fabric interface to the GTX transceiver can be either 32 or 40 bits wide and selectable at generate time Polarity The polarity of the TX side of each GTX transceiver can be changed at runtime Reset Ea...

Страница 25: ...A fabric interface to the GTH transceiver can be either 32 or 40 bits wide and selectable at generate time Polarity The polarity of the TX side of each GTH transceiver can be changed at runtime Reset...

Страница 26: ...bric interface to the GTP transceiver can be either 32 or 40 bits wide and selectable at generate time Polarity The polarity of the TX side of each GTP transceiver can be changed at runtime Reset Each...

Страница 27: ...abric Width The FPGA fabric interface to the GTZ transceiver can only be 160 bits wide Polarity The polarity of the TX side of each GTZ transceiver can be changed at runtime Reset Each GTZ transceiver...

Страница 28: ...alled on your system Tcl stands for Tool Command Language and a Tcl shell is a shell program that is used to run Tcl scripts CSE Tcl requires the Tcl shell called xtclsh that is included in the ChipSc...

Страница 29: ...test Downloads at speeds up to 12 Mb s throughput Contains an adjustable voltage interface that enables it to communicate with systems and device I Os operating at 5V down to 1 5V Windows and Red Hat...

Страница 30: ...gnals are required to disable these sources preventing contention with the download cable If using the Parallel Cable IV Platform Cable USB Digilent JTAG HS1 or ByteTools download cable then VREF 1 5...

Страница 31: ...ctions of the browser You can also find the ChipScope Pro cores by using the View by Name tab Note Core instantiation templates for the ChipScope Pro cores are found in the vho file for VHDL language...

Страница 32: ...ort documentation click the IP tab and search under Embedded Processing Debug and Trace DS774 LogiCORE IP ChipScope Pro IBERT for Virtex 5 GTX FPGA Transceivers DS732 LogiCORE IP ChipScope Pro IBERT f...

Страница 33: ...ity has been incorporated into the PlanAhead tool environment To make it easier to migrate from the ChipScope Pro Core Inserter tool to the ISE PlanAhead tool environment a CDC import command is provi...

Страница 34: ...rocesses as necessary and then opens the cdc file in the ChipScope Pro Core Inserter tool 3 Modify the cores and connections in the ChipScope Pro Core Inserter tool as necessary as shown in ChipScope...

Страница 35: ...CDC Project 2 Editing the CDC Project 3 Inserting Cores The ChipScope Pro Core Inserter is invoked prior to calling ngdbuild to instantiate debug cores in the design Nets are selected for debug using...

Страница 36: ...tep does not bring up the ChipScope Pro Core Inserter graphical user interface GUI X Ref Target Figure 3 1 Figure 3 1 Command Line Core Inserter Flow Start Done Design Entry Design Synthesis Device Pr...

Страница 37: ...is inserter edit project cdc ngcbuild p partname sd source_dir dd output_dir i inputdesign edn ngc outputdesign ngc Insert Cores Step The Insert Cores step of the command line ChipScope Pro Core Inser...

Страница 38: ...recently opened projects or select File Open Project and Browse to the project location After you locate the project you can either double click it or click Open Saving Projects If a project has chan...

Страница 39: ...tlist 2 Click Browse to navigate to the directory where the netlist resides 3 Modify the Output Design Netlist and Output Directory fields as needed These fields are automatically filled in initially...

Страница 40: ...evice families and the variants of these families The BRAM Count core utilization feature is available for all supported device families Choosing ICON Options The first options that must be specified...

Страница 41: ...n equation to be a combination of multiple match units However increasing the number of match units per trigger port also increases the usage of logic resources accordingly Note The aggregate number o...

Страница 42: ...ndition Sequencer The trigger condition sequencer is a standard Boolean equation trigger condition that can be augmented with an optional trigger sequencer by checking the Enable Trigger Sequencer Ran...

Страница 43: ...ecide whether or not to capture and store each individual data sample The trigger and storage qualification conditions can be used together to define when to start the capture process and what data to...

Страница 44: ...ample word width of 4 096 bits or 256 bits for Spartan 3 Spartan 3E Spartan 3A Spartan 3A DSP and Virtex 4 devices Data Separate from Trigger checked OFF The data port is completely independent of the...

Страница 45: ...configuration This mode makes it possible to capture events that immediately follow device configuration without having to first set up the ATC2 core manually This feature is disabled by default and i...

Страница 46: ...instantiated inside the ATC2 core for your convenience This means that although you do not have to bring the ATCK and ATD pins through every level of hierarchy to the top level of your design manually...

Страница 47: ...sponding signal name in the HDL source due to renaming and other optimizations during synthesis Source Instance The instance name of the lower level hierarchical component from which the net at the cu...

Страница 48: ...sen in this fashion After you have chosen all the nets for a given bus the ILA or ATC2 bus name changes from red to black After specifying the clock trigger and data nets click Insert If you are using...

Страница 49: ...y called _ngo If a valid ISE _ngo directory is found the ChipScope Pro Core Inserter project is automatically set up to overwrite the intermediate NGD files of the ISE project with those produced by t...

Страница 50: ...50 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v14 3 October 16 2012 Chapter 3 Using the ChipScope Pro Core Inserter...

Страница 51: ...ion that connects to the JTAG chain of the target system using any of the supported JTAG download cables shown in Table 1 13 page 29 The ChipScope Pro Analyzer client is a graphical user interface GUI...

Страница 52: ...of the window Message pane at the bottom of the window Main window area Both the project tree signal browser split pane and the Message pane can be hidden by deselecting those options in the View men...

Страница 53: ...All to View menu options Selected signals and buses can be added through the Add to View menu options To select a contiguous group of signals and buses click the first signal hold down the Shift key...

Страница 54: ...gned decimal value that is modified using the following equations Bus Value scale factor Data offset Precision precision Whether the selected bus radix is Signed Decimal or Unsigned Decimal a dialog b...

Страница 55: ...ter in a token file is The first non comment line of the token file must be FILE_VERSION 1 0 0 Note The sign is a reserved character and cannot be part of the TOKEN string Below is an example token fi...

Страница 56: ...xisting project select File Open Project or select one of the recently used projects in the File menu The title bar of the ChipScope Pro Analyzer and the project tree displays the project name If the...

Страница 57: ...in the entire core unit Selected Print waveform data for only those signals and buses that are currently selected in the waveform window The default prints waveform data using the Current View method...

Страница 58: ...ge Preview Buttons The buttons at the top of the page control which page of the waveform printout is being previewed as follow The and buttons go to the first and last preview pages respectively The a...

Страница 59: ...Editor tools can create such files To import signal names from a file select File Import A Signal Import dialog box appears To select the signal import file choose Select New File A file dialog box a...

Страница 60: ...cal mode the Password setting is not necessary Note In local mode the server starts automatically For remote mode operation the Server setting must be set to an IP address or appropriate system name a...

Страница 61: ...ation of USB21 the second cable is assigned USB22 and so on For newer Platform Cable USB download cables the unique electronic serial number ESN that is read from the cable is displayed Note The enume...

Страница 62: ...with a particular physical Platform Cable USB cable This means that rebooting your machine might result in different associations between enumerations and physical cables One work around is to unplug...

Страница 63: ...FPGA CPLD PROM and System ACE devices are automatically detected The entire IDCODE can be verified for valid target devices To view the chain composition select JTAG Chain JTAG Chain Setup A dialog bo...

Страница 64: ...o the JTAG Configuration dialog box You can also automatically create buses from the signal names found in the CDC file by selecting the Auto create buses check box The ChipScope Pro Analyzer tool use...

Страница 65: ...combination Windows cannot be closed from this dialog box The same operation can by achieved by double clicking on the Trigger Setup leaf node in the project tree or by right clicking on the Trigger...

Страница 66: ...r condition occurs Valid values are any positive integer from 1 to the depth of the capture buffer The trigger mark always appears as sample 0 in the window As many sample windows as possible are capt...

Страница 67: ...igger characters Valid characters for the different radices are Hex X 0 9 and A F X indicates that all four bits of that nibble are don t cares The character indicates that the nibble consists of a mi...

Страница 68: ...on is the currently active one Trigger Condition Name Field The Trigger Condition Name field provides a mnemonic for a particular trigger condition Trigger Condition n is used by default Trigger Condi...

Страница 69: ...igger event Pulse Low The output is a single clock cycle pulse of logic 0 10 cycles after the trigger event Level High The output transitions from a 0 to a 1 10 cycles after the trigger event Level Lo...

Страница 70: ...lost Trigger Run Modes The ChipScope Pro Analyzer tool supports three trigger run modes for the ILA core Single Repetitive Startup The trigger run mode is selected by using either the Trigger Setup Tr...

Страница 71: ...Fast Binary Data Format FBDF To select a format click its radio button Use the Signals to Export combo box to select the set of signals and or buses to export The signals that can be exported include...

Страница 72: ...igger condition has occurred first change the Trigger Run Mode to Startup The software prompts you to specify the startup trigger files that were used during the implementation process to create the B...

Страница 73: ...us in the Bus Signal column Bus and Signal Reordering Buses and signals can be reordered in the Waveform window Select one or more signals and buses and drag it to its new location A red line shows th...

Страница 74: ...indow default or by the overall sample number in the buffer To display the sample number starting over at 0 for each window select Ruler Sample in Window in the right click menu To display the sample...

Страница 75: ...column and drag it to the new location Go to Cursors To automatically scroll the listing view to a cursor right click and select Go To Go To X Cursor or Go To Go To O Cursor Bus Plot Window To view t...

Страница 76: ...is for VIO cores only To open the Console for a particular VIO core double click the VIO Console leaf node in the project tree Here you can see the status and activity of the VIO core input signals a...

Страница 77: ...ignals and Buses Individual signals and buses can be cut copied pasted or deleted using right click menus Either right click a signal or bus and select the operation desired or use the standard Window...

Страница 78: ...dialog box One text field is available for each cycle in the pulse train The text fields are populated by default according to the last value of the bus or signal For buses the fields are always disp...

Страница 79: ...itor User Guide See Reference 22 p 225 Virtex 6 FPGA System Monitor User Guide See Reference 23 p 225 7 Series FPGAs XADC Dual 12 Bit 1MSPS Analog to Digital Converter User Guide See Reference 13 p 22...

Страница 80: ...selectable via a combo box The default scan rate is 1 s You can also set the sample period to 1 s 2 s 5 s 10 s 30 s 1 min or Manual Scan When Manual Scan is chosen the Sample Once S button becomes en...

Страница 81: ...consumes a large amount of disk space To alleviate the problem the log data can be split across multiple separate files based on a log file limit The log file limit can be based on a specific number o...

Страница 82: ...End PMA The circuit originates and ends at some external channel endpoint for example external test equipment or another device but passes through the part of the GTX transceiver channel For this GTX...

Страница 83: ...resets the bit error and received bit counters It is appropriate to reset the BERT counters after the GTX channel is linked and stable Clocking Settings The TX DCM Reset button resets the DCM that use...

Страница 84: ...in binary Some ports are read only and not editable Those cells in the table look like labels The ports in the table that are editable look like text fields and placing the cursor in those fields typi...

Страница 85: ...en the Up or Down buttons To revert the sweep attributes and their order to the default setting click the Reset to Default button Click OK to apply the settings or Cancel to exit without saving Sampli...

Страница 86: ...are available If File is enabled click Browse to specify the file destination The third screen is the confirmation screen summarizing the source and destination s for the settings Click Apply to execu...

Страница 87: ...in the near end GTX transceiver channel It starts at the TX fabric interface passes through the PCS and returns immediately to the RX fabric interface without ever passing through the PMA side of the...

Страница 88: ...7 15 23 and 31 and Clk 2x and 10x The RX Bit Error Ratio field contains the currently calculated bit error ratio for the GTX transceiver channel It is expressed as an exponent For instance 1 000E 12 m...

Страница 89: ...Settings panel contains a table that is made up of one or more vertical columns and horizontal rows Each column represents a specific active GTX transceiver Each row represents a specific MGT port Not...

Страница 90: ...add new parameters to sweep click it in the left hand list and click the arrow button To remove a parameter to sweep click it in the right hand list and click the arrow button To specify the sweep or...

Страница 91: ...ed bit error ratio BER The horizontal marker can be moved up and down and the vertical markers can be moved left and right by clicking and dragging them By right clicking in the plot list area on the...

Страница 92: ...wse and navigate to the settings file Click Next to go to the next screen The second screen is the destination screen Any combination of the MGTs in the IBERT design and a file are available If File i...

Страница 93: ...o feedback path is used Near End PCS The circuit is wholly contained within the near end GTH transceiver channel It starts at the TX fabric interface passes through the PCS and returns immediately to...

Страница 94: ...s specified at compile time DRP Settings Panel The DRP Settings panel contains a table displaying the DRP attributes or addresses Each column represents a specific active GTH QUAD because there is one...

Страница 95: ...p Parameter table dictates how the parameters are swept The values of the parameters near the top of the table are swept less frequently than the parameters near the bottom of the table In other words...

Страница 96: ...s the file limit multiple files with starting iteration number appended to the base file name are created in the same directory as the initial result file Test Results The Test Results panel identifie...

Страница 97: ...tion Use the Check All and Uncheck All buttons to select all or none of the transceivers The right hand panel selects which rows are displayed in the MGT BERT settings Use the Check All and Uncheck Al...

Страница 98: ...ntains a table that is made up of one or more vertical columns and horizontal rows Each column represents a specific active GTP Transceiver Each row represents a specific control or status setting MGT...

Страница 99: ...the GTP transceiver channel To flip the polarity of the TX side of the GTP transceiver check the TX Polarity Invert box The TX Bit Error Inject button inverts the polarity of a single bit in a single...

Страница 100: ...compile time DRP Settings Panel The DRP Settings panel contains a table that is made up of one or more vertical columns and horizontal rows Each column represents a specific active GTP transceiver Eac...

Страница 101: ...ter table dictates how the parameters are swept The values of the parameters near the top of the table are swept less frequently than the parameters near the bottom of the table In other words the par...

Страница 102: ...as the initial result file Test Results The Test Results panel shows the current iteration the elapsed time and the estimated time remaining Below this status information are the test results for eac...

Страница 103: ...for 7 Series FPGA GTX Transceivers To open the console for a ChipScope Pro IBERT core for Virtex 7 Kintex 7 FPGA GTX transceivers select Window New Unit Windows and the core desired A dialog box disp...

Страница 104: ...device but passes through part of the GTX transceiver channel For this GTX loopback mode the signal comes into the RX pins passes through the PMA through the PCS back through the PMA and returns to th...

Страница 105: ...panel contains a table that is made up of one or more vertical columns and horizontal rows Each column represents a specific active GTX transceiver Each row represents a specific DRP attribute or addr...

Страница 106: ...right arrow button to add it to the list on the right To remove a parameter to sweep first select it in the right hand list and click the left arrow button To specify the sweep order of the parameter...

Страница 107: ...is scanned Test Controls After the sweep test has been set up the test can be started by clicking the Start button After the Start button is clicked the sweep parameter table is disabled and the test...

Страница 108: ...correspond to the Horizontal settings in the Scan Settings panel In 1D Bathtub mode the main measurement that is observed in the sweep test plot is the width of the UI opening of the active plot at th...

Страница 109: ...settings file The second wizard screen is the destination screen Any combination of the MGTs in the IBERT design and a file are available If File is enabled click Browse to specify the file destinati...

Страница 110: ...l It starts at the TX fabric interface passes through the PCS and returns immediately to the RX fabric interface without ever passing through the PMA side of the GTH channel Near End PMA the circuit i...

Страница 111: ...select the data pattern that is used by the transmit pattern generator and receive pattern checker respectively These patterns include PRBS 7 15 23 and 31 and Clk 2x and 10x The BERT Settings also in...

Страница 112: ...erformed when the corresponding TX endpoint for the link resides in a different device or a different transceiver in the same device The tabbed Sweep Test Settings panel consists of four sections MGT...

Страница 113: ...n and the Offset Sample location match then this is not considered an error However if the two bit values do not match then this is considered an error bit causing the bit error ratio BER to increase...

Страница 114: ...set sample point Use the selection buttons in the Plot List area on the right side of the Sweep Test Plots panel to show one plot at a time Use the right click menu options to rename the plot Below th...

Страница 115: ...tion Use the Check All and Uncheck All buttons to select all or none of the MGTs The right panel selects which rows are displayed in the MGT BERT settings The Default button sets up the Console to dis...

Страница 116: ...rtical columns and horizontal rows Each column represents a specific active GTP transceiver Each row represents a specific control or status setting MGT Settings The MGT Alias setting is initially set...

Страница 117: ...t out of the TX pins of the GTP transceiver channel To change the polarity of the TX side of the GTP transceiver check the TX Polarity Invert box The TX Bit Error Inject button inverts the polarity of...

Страница 118: ...in the text field where the value is type in a new value and press Enter The new value is immediately set in the MGT Port Settings Panel The Port Settings panel contains a table that is made up of on...

Страница 119: ...In other words the parameters near the top of the table are in the outer loops of the sweep algorithm while the parameters near the bottom of the table are in the inner loops of the sweep algorithm Ea...

Страница 120: ...a particular scan offset location Use the BER option to specify the lowest bit error ratio that should be achieved before moving to the next scan offset Use the Time option to specify how much time s...

Страница 121: ...nel Check to show uncheck to hide Plot Name name of the plot Click the text field to change plot name In 1D Bathtub scan algorithm mode the table columns correspond to the following Enable Plot shows...

Страница 122: ...Manual Scan When Manual Scan is selected use IBERT_A7GTP Scan Now or the Scan Now or S toolbar button to query the IBERT core IBERT Console Window for 7 Series FPGA GTZ Transceivers To open the consol...

Страница 123: ...he TX Bit Error Inject button inverts the polarity of a single bit in a single transmitted word The receiver endpoint of the channel that is connected to this transmitter should detect a single bit er...

Страница 124: ...nary Some ports are read only and not editable Those cells in the table look like labels The ports in the table that are editable look like text fields and placing the cursor in those fields typing a...

Страница 125: ...set the start and end values for that parameter to the same value The Sweep Value Count column indicates how many values are swept through for a particular parameter After all sweep parameters have v...

Страница 126: ...SV log file If the 2D Full Scan algorithm is used each plot corresponds to a sweep across the horizontal and the vertical ranges specified in the Scan Settings panel The color of the plot region corre...

Страница 127: ...to select which columns and rows to display in the IBERT Console The left panel selects the MGTs by location Use the Check All and Uncheck All buttons to select all or none of the MGTs The right panel...

Страница 128: ...r You can use the standalone IBERT sweep test plot viewer to view CSV sweep test result files that were created by running IBERT sweep tests on the following transceivers Spartan 6 FPGA GTP transceive...

Страница 129: ...ipScope Pro Analyzer tool can be started either from the command line or from the Start menu On 32 bit Windows systems you can invoke the ChipScope Pro Analyzer tool from the command line by running X...

Страница 130: ...ipScope Pro Analyzer tool exits The default is userprofile chipscope cs_analyzer ini log path and filename log stdout Write log messages to the specified file Specifying stdout writes to standard outp...

Страница 131: ...nce 14 p 225 A supported JTAG cable such as Platform Cable USB Parallel Cable IV or Parallel Cable III A Tcl shell xtclsh is provided in the ChipScope Pro and ISE tool installations or the ActiveTcl 8...

Страница 132: ...a Tcl Commands page 134 CseCore ChipScope Pro core status commands see CseCore Tcl Commands page 136 CseVIO ChipScope Pro VIO core status and control commands see CseVIO Tcl Commands page 136 Table 5...

Страница 133: ...arsing a Boundary Scan Description Language BSDL buffer parse_bsdl_file Extracts device data for a JTAG device by parsing a Boundary Scan Description Language BSDL file Table 5 5 Summary of chipscope...

Страница 134: ...IR length of a device get_device_idcode Gets the IDCODE of a device set_device_idcode Sets the IDCODE of a device navigate Navigates to a JTAG TAP state shift_chain_ir Shifts a stream of bits into and...

Страница 135: ...tus of an FPGA device chipscope csefpga_is_sys_mon_supported Tests if System Monitor commands are supported for the target FPGA device chipscope csefpga_run_sys_mon_command_sequence Executes a sequenc...

Страница 136: ..._core_status Retrieves the static status word from the target ChipScope Pro core chipscope csecore_is_cores_supported Tests if a the target FPGA device supports ChipScope Pro cores Table 5 9 CseVIO Tc...

Страница 137: ...chipscope csejtag_target get_pin chipscope csejtag_target pulse_pin chipscope csejtag_target wait_time chipscope csejtag_target get_info chipscope csejtag_tap autodetect_chain chipscope csejtag_tap in...

Страница 138: ...d fails Example 1 Create a new session with no optional arguments set handle chipscope csejtag_session create messageRouterFn 2 Create a new session using the client server libraries to a server calle...

Страница 139: ...rsion of the CseJtag API library Syntax chipscope csejtag_session get_api_version Arguments There are no arguments for this command Returns A Tcl list containing API version information List elements...

Страница 140: ...he command fails Example Send the message Hello World to the message router function chipscope csejtag_session send_message handle CSE_MSG_INFO Hello World Back to list of all CseJtag Tcl Commands Tab...

Страница 141: ...me of the JTAG target to open See Table 5 14 for available targetName and optional args combinations If targetName is set to CSEJTAG_TARGET_AUTO then the first available JTAG cable target is opened pr...

Страница 142: ...with a frequency of 200000 Returns information on the opened target set targetInfo chipscope csejtag_target open handle CSEJTAG_TARGET_PARALLEL progressFunc port LPT1 frequency 200000 Back to list of...

Страница 143: ...ope csejtag_target close handle Arguments Returns An exception is thrown if the subcommand fails Example Close the current target in the specified session chipscope csejtag_target close handle Back to...

Страница 144: ...nts Returns Connection status 1 indicates connection to target is open and active 0 indicates closed An exception is thrown if the subcommand fails Example Return current target in the specified sessi...

Страница 145: ...D_ME CSEJTAG_LOCKED_OTHER CSEJTAG_UNKNOWN An exception is thrown if the subcommand fails Example Attempt to obtain an exclusive target lock and wait at least 1000 milliseconds Obtains the status of th...

Страница 146: ...AG target device Syntax chipscope csejtag_target unlock handle Arguments Returns An exception is thrown if the subcommand fails Example Unlock the target in the specified session chipscope csejtag_tar...

Страница 147: ...atus of the lock in the form of one of the following CSEJTAG_LOCKED_ME CSEJTAG_LOCKED_OTHER CSEJTAG_UNKNOWN An exception is thrown if the subcommand fails Example Obtain the current lock status set lo...

Страница 148: ...only cleans up locks for JTAG cable targets Syntax chipscope csejtag_target clean_locks handle Arguments Returns An exception is thrown if the subcommand fails Example Clean locks as a last resort bec...

Страница 149: ...subcommand before calling this subcommand Syntax chipscope csejtag_target flush handle Arguments Returns An exception is thrown if the subcommand fails Example Attempt to flush an opened and locked bu...

Страница 150: ...cope csejtag_tap subcommands use the chipscope csejtag_tap navigate subcommand to set the JTAG TAP state machine to the CSEJTAG_TEST_LOGIC_RESET state Syntax chipscope csejtag_target set_pin handle pi...

Страница 151: ...command Syntax chipscope csejtag_target get_pin handle pin Arguments Returns JTAG TAP pin value 1 set 0 clear An exception is thrown if the subcommand fails Example Get the current value of the TDO pi...

Страница 152: ...cope csejtag_tap subcommands use the chipscope csejtag_tap navigate subcommand to set the JTAG TAP state machine to the CSEJTAG_TEST_LOGIC_RESET state Syntax chipscope csejtag_target pulse_pin handle...

Страница 153: ...mand Syntax chipscope csejtag_target wait_time handle usecs Arguments Returns An exception is thrown if the subcommand fails Example Instruct the JTAG target to wait 1000 microseconds before performin...

Страница 154: ...le Obtain information about the current JTAG target set targetInfo chipscope csejtag_target get_info handle Back to list of all CseJtag Tcl Commands Table 5 26 Arguments for Subcommand chipscope csejt...

Страница 155: ...Returns An exception is thrown if the subcommand fails to detect the chain completely In the case of such an error the devices in the JTAG chain must be detected and assigned manually Example Attempt...

Страница 156: ...ample Attempt to interrogate the chain using the default algorithm chipscope csejtag_tap interrogate_chain handle CSEJTAG_SCAN_DEFAULT Back to list of all CseJtag Tcl Commands Table 5 28 Arguments for...

Страница 157: ...calling this subcommand Syntax chipscope csejtag_tap get_device_count handle Arguments Returns The number of devices in the chain An exception is thrown if the subcommand fails Example Obtain the numb...

Страница 158: ...before calling this subcommand Syntax chipscope csejtag_tap set_device_count handle count Arguments Returns An exception is thrown if the subcommand fails Example Set the number of devices in the JTA...

Страница 159: ...mmand Note The JTAG target must be locked by using the chipscope csejtag_target lock subcommand before calling this subcommand Also the device count must be set prior to calling this subcommand using...

Страница 160: ...CODE command Note The JTAG target must be locked by using the chipscope csejtag_target lock subcommand before calling this subcommand Also the device count must be set prior to calling this subcommand...

Страница 161: ...ing this subcommand using the chipscope csejtag_tap set_device_count Syntax chipscope csejtag_tap get_device_idcode handle deviceIndex Arguments Returns A 32 character string of ones and zeros represe...

Страница 162: ...chipscope csejtag_tap set_device_count Syntax chipscope csejtag_tap set_device_idcode handle deviceIndex idcode Arguments Returns An exception is thrown if the subcommand fails Example Set the IDCODE...

Страница 163: ...exception is thrown if the subcommand fails Example Navigate the TAP state to Test Logic Reset and keep it in this state for five additional clock cycles chipscope csejtag_tap navigate handle CSEJTAG_...

Страница 164: ...Required Handle to the session that is returned by chipscope csejtag_session create shiftMode CSJTAG_SHIFT_READ CSJTAG_SHIFT_WRITE CSJTAG_SHIFT_READWRITE exitState Statetoendinaftershiftiscomplete CS...

Страница 165: ...unction shifts in 64 ones into the instruction register captures the 64 bits of received data and navigates to the Run Test Idle state when finished set hextdobuf chipscope csejtag_tap shift_chain_ir...

Страница 166: ...Arguments for Subcommand chipscope csejtag_tap shift_device_ir Argument Type Description handle Required Handle to the session that is returned by chipscope csejtag_session create deviceIndex Device i...

Страница 167: ...An exception is thrown if the subcommand fails Example This function shifts in 11 ones into the instruction register of the device at index 1 captures the 11 bits of received data and navigates to th...

Страница 168: ...Handle to the session that is returned by chipscope csejtag_session create shiftMode CSJTAG_SHIFT_READ CSJTAG_SHIFT_WRITE CSJTAG_SHIFT_READWRITE exitState State to end in after shift is complete CSEJT...

Страница 169: ...unction shifts in 64 ones into the instruction register captures the 64 bits of received data and navigates to the Run Test Idle state when finished set hextdobuf chipscope csejtag_tap shift_chain_dr...

Страница 170: ...or Subcommand chipscope csejtag_tap shift_device_dr Argument Type Description handle Required Handle to the session that is returned by chipscope csejtag_session create deviceIndex Device index 0 to n...

Страница 171: ...TAP An exception is thrown if the subcommand fails Example This function shifts in 11 ones into the data register of the device at index 1 captures the 11 bits of received data and navigates to the R...

Страница 172: ...e subcommand fails Example Adding data from the file my_idcode lst to the internal device database Also store the data record buffer and buffer size in local variables chipscope csejtag_db add_device_...

Страница 173: ...f bits in the IR of the device cmd_bypass String containing the BYPASS instruction for the device usually all ones An exception is thrown if the subcommand fails Example Look in the database for the d...

Страница 174: ...g containing the device name An exception is thrown if the subcommand fails Example Look in the database for the name of the device belonging to IDCODE 01010101010101010101010101010101 set deviceName...

Страница 175: ...the size of the IR in bits An exception is thrown if the subcommand fails Example Look in the database for the IR length of the device belonging to IDCODE 01010101010101010101010101010101 set irlen ch...

Страница 176: ...of the device cmd_bypass String containing the BYPASS instruction for the device usually all ones An exception is thrown if the subcommand fails Example Extract device information from the file device...

Страница 177: ...aining the name of the device irlen Number of bits in the IR of the device idcode IDCODE of the device cmd_bypass String containing the BYPASS instruction for the device usually all ones An exception...

Страница 178: ...csefpga_configure_device chipscope csefpga_configure_device_with_file chipscope csefpga_get_config_reg chipscope csefpga_get_instruction_reg chipscope csefpga_get_usercode chipscope csefpga_get_user_c...

Страница 179: ...e Do not remove Windows unix end of line characters from fileData fileDataByteLen Required Length of fileData byte array in bytes optional args Optional Enables additional device configuration options...

Страница 180: ...s verify_internal_done verify_internal_done true verify_internal_done false Read internal device DONE status after configuration from the device JTAG instruction register Default is verify_internal_do...

Страница 181: ...e mydesign bit set configStatus chipscope csefpga_configure_device handle 2 fileName CSE_DEFAULT_OPTIONS progressCallBack Back to list of all CseFpga Tcl Commands Table 5 48 Arguments for Subcommand c...

Страница 182: ...Buf A comma separated list of strings that represent configuration register bit names An exception is thrown if the command fails Example Read the contents of the configuration register of the third d...

Страница 183: ...imal bitNameBuf A comma separated list of strings that represent configuration register bit names An exception is thrown if the command fails Example Read the contents of the configuration register of...

Страница 184: ...s of the USERCODE register in hexadecimal An exception is thrown if the command fails Example Read the contents of the USERCODE register of the third device in the JTAG chain set usercode csefpga_get_...

Страница 185: ...in the device 0 if the device does not have any USER scan chain registers An exception is thrown if the command fails Example Get the number of USER scan chain registers supported by the device to whi...

Страница 186: ...vice referred to by idcode is supported by the csefpga_configure_device command otherwise returns 0 An exception is thrown if the command fails Example Determine if the device referred to by idcode ca...

Страница 187: ...o by deviceIndex is configured otherwise returns 0 An exception is thrown if the command fails Example Get the configuration status of the third device in the JTAG chain set isConfigured csefpga_is_co...

Страница 188: ...e device referred to by idcode contains a System Monitor block otherwise returns 0 An exception is thrown if the command fails Example Determine if the device referred to by idcode contains a System M...

Страница 189: ...list 10 11 list 55AA 0000 list 1 0 2 Back to list of all CseFpga Tcl Commands Table 5 56 Arguments for Subcommand chipscope csefpga_run_sys_mon_command_sequence Argument Type Description handle Requi...

Страница 190: ...s hexAddress An exception is thrown if the command fails Example For the second device in the JTAG chain read the System Monitor register at address 0x07 set hexOutData csefpga_get_sys_mon_reg handle...

Страница 191: ...TAG chain write 0xABCD to the System Monitor register at address 0x09 csefpga_set_sys_mon_reg handle 1 9 abcd Back to list of all CseFpga Tcl Commands Table 5 58 Arguments for Subcommand chipscope cse...

Страница 192: ...hain register Syntax chipscope csecore_get_core_count handle deviceIndex userRegNumber Arguments Returns The number of cores An exception is thrown if the command fails Example Get the number of cores...

Страница 193: ...on the second USER register set coreRef list 3 2 0 set coreStatus csecore_get_core_status handle coreRef Back to list of all CseCore Tcl Commands Table 5 60 Arguments for Subcommand chipscope csecore...

Страница 194: ...evice referred to by idcode supports ChipScope Pro cores otherwise returns 0 An exception is thrown if the command fails Example Determine if device referred to by idcode supports ChipScope Pro cores...

Страница 195: ...tus word from the target VIO core Syntax chipscope csevio_get_core_info handle list deviceIndex userRegNumber coreIndex coreInfoTclArray Arguments Table 5 62 Arguments for Subcommand chipscope csevio_...

Страница 196: ...Element Description manufacturerId Manufacturer ID integer CSEVIO_MANUFACTURER_ID Manufacturer s ID 1 for Xilinx CSEVIO_CORE_TYPE Core Type field different for each ChipScope Core VIO should be 9 CSEV...

Страница 197: ...rst core connected to ICON core inside fourth device on second USER register is a VIO core set coreRef list 3 2 0 set isVIO csevio_is_vio_core handle coreRef Back to list of all CseVIO Tcl Commands Ta...

Страница 198: ...re connected to ICON core inside fourth device on second USER register is a VIO core set coreRef list 3 2 0 csevio_init_core handle coreRef Back to list of all CseVIO Tcl Commands Table 5 64 Arguments...

Страница 199: ...connected to ICON core inside fourth device on second USER register is a VIO core set coreRef list 3 2 0 csevio_terminate_core handle coreRef Back to list of all CseVIO Tcl Commands Table 5 65 Argumen...

Страница 200: ...ist of all CseVIO Tcl Commands Table 5 66 Arguments for Subcommand chipscope csevio_define_signal Argument Type Description handle Required Handle to the session that is returned by chipscope csejtag_...

Страница 201: ...o list of all CseVIO Tcl Commands Table 5 67 Arguments for Subcommand chipscope csevio_define_bus Argument Type Description handle Required Handle to the session that is returned by chipscope csejtag_...

Страница 202: ...ist 3 2 0 set csevio_undefine_name handle coreRef control_bus CSEVIO_SYNC_OUTPUT Back to list of all CseVIO Tcl Commands Table 5 68 Arguments for Subcommand chipscope csevio_undefine_name Argument Typ...

Страница 203: ...Tcl Commands Table 5 69 Arguments for Subcommand chipscope csevio_write_values Argument Type Description handle Required Handle to the session that is returned by chipscope csejtag_session create list...

Страница 204: ...s Argument Type Description handle Required Handle to the session that is returned by chipscope csejtag_session create list deviceIndex userRegNumber coreIndex A list containing three elements Device...

Страница 205: ...linx ISE Design Suite or in the ActiveTcl 8 4 Tcl shell tclsh from ActiveState Software Inc See Reference 24 p 226 To run the Tcl example in a command line shell change to the directory where csejtag_...

Страница 206: ...3 October 16 2012 Chapter 5 ChipScope Engine Tcl Interface Other example Tcl scripts such as the CSE VIO example Tcl script called csevio_example1 tcl can be found in the same directory as csejtag_ex...

Страница 207: ...rors and issues you might face when using the ChipScope Pro tools In addition this appendix provides a general practices for troubleshooting your ChipScope Pro and Xilinx JTAG based programming cable...

Страница 208: ...lation directory for ChipScope Pro tools to operate correctly On Windows systems select Start Settings Control Panel System Advanced System Variables Set the environment variable XILINX to point to yo...

Страница 209: ...verifying correct cable connections see Table A 3 page 211 For troubleshooting issues related to INFO Cable connection failed messages see Table A 4 page 211 For troubleshooting issues related to ERR...

Страница 210: ...01 INFO Opened socket connection localhost 50001 localhost 127 0 0 1 INFO Connecting to cable Usb Port USB21 INFO Checking cable driver INFO Driver file xusbdfwu sys found INFO Driver version src 1027...

Страница 211: ...bit SYS 12 35 07 version 811 INFO LPT base address 0378h INFO ECP base address 0778h INFO ECP hardware is detected INFO Cable connection established INFO Connecting to cable Parallel Port LPT1 in ECP...

Страница 212: ...hain Platform Cable USB In the dialog box check to make sure that the Port setting is set to the correct port enumeration for the desired cable For instance for the first enumerated cable select port...

Страница 213: ...if target voltage is in the proper range and applied to the correct pin The issue here is usually an incorrect voltage on the VCC Go to Issue 2 2 Is the target board powered on If NO Check that the b...

Страница 214: ...t Modify connections so that you have a valid chain A different ribbon cable or fly leads for connection might help Alternatively a different board might not have the issue If YES Go to Issue 3 3 Is s...

Страница 215: ...o obtain the resistor value Spartan 3 FPGA Configuration User Guide See Reference 7 p 225 Spartan 6 FPGA Configuration User Guide See Reference 8 p 225 Virtex 4 FPGA Configuration User Guide See Refer...

Страница 216: ...your system is denying access to the port socket Go to Issue 2 2 Are you running any firewall applications that might prevent the ChipScope Pro Analyzer tool from connecting to a TCP IP socket If YES...

Страница 217: ...pScope Pro Analyzer tool polls the JTAG chain for a status word that indicates the number and type s of core s in the device The reading of the status word can result in corrupt date either by noise o...

Страница 218: ...pj file immediately after ChipScope Pro Analyzer tool launches before any other action If NO Go to Issue 5 5 Are there any non Xilinx devices in the JTAG chain If YES You must enter the instruction re...

Страница 219: ...8 Have the core constraints being applied correctly If NO or NOT SURE Check that a PERIOD constraint has been added to the clock used as the Clock for your ILA If there is no constraint on this net in...

Страница 220: ...clock is running but your trigger condition never occurs In the Trigger Setup windows ensure that you have set the condition correctly if you are certain that this event the trigger condition happens...

Страница 221: ...the NCF file associated with the core was applied If the core netlist file ngc ngo was moved during implementation the associated constraint file ncf might not have been moved accordingly If YES Go to...

Страница 222: ...y be corrupt message can appear You must re implement your design ensuring that this attribute is set for your ICON generation If YES Go to Issue 4 4 Have the core constraints been applied correctly I...

Страница 223: ...cs_analyzer log file is stored in your homepath chipscope directory This location is typically the same as C Documents and Settings username chipscope On Linux The cs_analyzer log file is stored in y...

Страница 224: ...224 www xilinx com ChipScope Pro Software and Cores User Guide UG029 v14 3 October 16 2012 Appendix A ChipScope Pro Tools Troubleshooting Guide...

Страница 225: ...2 Spartan 3 Generation Configuration User Guide 8 UG380 Spartan 6 FPGA Configuration User Guide 9 UG071 Virtex 4 FPGA Configuration User Guide 10 UG191 Virtex 5 FPGA Configuration User Guide 11 UG360...

Страница 226: ...Cores User Guide UG029 v14 3 October 16 2012 Appendix B References Other references 24 ActiveState 25 Agilent Technologies 26 Tcl Developer Xchange 27 Byte Tools 28 UG480 7 Series FPGAs XADC Dual 12 B...

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