14
ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1:
Introduction
Using Trigger and Storage Qualification Conditions
The ILA core implements both trigger and storage qualification condition logic. The
trigger condition is a Boolean or sequential combination of events that is detected by match
unit comparators that are attached to the trigger ports of the core. The trigger condition is
used to mark a distinct point of origin in the data capture window and can be located at the
beginning, the end, or anywhere within the data capture window.
Similarly, the storage qualification condition is also a Boolean combination of events that is
detected by match unit comparators that are subsequently attached to the trigger ports of
the core. However, the storage qualification condition differs from the trigger condition in
that it evaluates trigger port match unit events to decide whether or not to capture and
store each individual data sample. The trigger and storage qualification conditions can be
used together to define when to start the capture process and what data is captured.
In the ILA core example shown in
, suppose you want to do the
following:
•
Trigger on the first memory write cycle (CE = rising edge, WE = 1, OE = 0) to Address
= 0xFF0000;
•
Capture only memory read cycles (CE = rising edge, WE = 0, OE = 1) from Address =
0x23AACC where the Data values are between 0x00000000 and 0x1000FFFF;
To implement these conditions successfully, you would need to make sure that both the
TRIG0 and TRIG1 trigger ports each have two match units attached to them: one for the
trigger condition and one for the storage qualification condition. Here is how you would
set up the trigger and storage qualification equations and each individual match unit to
satisfy the conditions above:
•
Trigger Condition = M0 && M2, where:
−
M0[2:0] = CE, WE, OE = “R10” (where ‘R’ means “rising edge”)
−
M2[23:0] = Address = “FF0000”
•
Storage Qualification Condition = M1 && M3 && M4, where:
−
M1[2:0] = CE, WE, OE = “R01” (where ‘R’ means “rising edge”)
−
M3[23:0] = Address = “23AACC”
−
M4[31:0] = Data = in the range of 0x00000000 through 0x1000FFFF
The triggering and storage qualification capabilities of the ILA core allow you to locate and
capture exactly the information that you want without wasting valuable on-chip memory
resources.
ILA Trigger Output Logic
The ILA core implements a trigger output port called TRIG_OUT. The TRIG_OUT port is
the output of the trigger condition that is set up at runtime using the ChipScope Pro
Analyzer tool. The shape (level or pulse) and sense (active-High or active-Low) of the
trigger output can also be controlled at run-time. The latency of the TRIG_OUT port
relative to the input trigger ports is 10 clock cycles.
The TRIG_OUT port is very flexible and has many uses. You can connect the TRIG_OUT
port to a device pin in order to trigger external test equipment such as oscilloscopes and
logic analyzers. Connecting the TRIG_OUT port to an interrupt line of an embedded
PowerPC® or MicroBlaze™ processor can be used to cause a software event to occur. You
can also connect the TRIG_OUT port of one core to a trigger input port of another core in
order to expand the trigger and data capture capabilities of your on-chip debug solution.
