Xerox WorkCentre 385, Руководство по обслуживанию, Страница: 152 / 184

WorkCentre 385
Circuit Description
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7 - 18
Table 2: KS32C6100 Signal Descriptions
Signal PIN No. Type Description
MCLK 206 I External master clock input. It has a 50% duty cycle and an
operating frequency up to 33MHz.
CLKSEL 201 I Clock select. When CLKSEL is “1” (High level), MCLK is used
as internal master clock directly. When CLKSEL is “0” (Low
level), the external MCLK frequency is divided by two and then
used as the internal master clock.
nRSTO 194 O Reset signal output from watch dog timer.
nRESET 195 I Not reset. nRESET is the global reset input for the
KS32C6100. To reset system, nRESET must be held to Low
level for at least 65 machine cycles.
nBK0HW 198 I Bank 0 data bus width select. When nB0HW is “0”, the bank 0
data bus is recognized as 16-bit wide. When nB0HW is “1”, the
bank 0 data bus is recognized as 32-bit wide.
TMODE 197 I Test pin. For normal operation, this pin should be connected to
GND.
TCK 208 I TAP controller clock.
TMS 204 I TAP controller mode select.
TDI 202 I TAP controller data input.
TDO 203 O TAP controller data output.
TnRST 196 I TAP controller reset signal.
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