WM8580
Production
Data
w
PD, Rev 4.7, March 2009
16
CONTROL INTERFACE TIMING – 2-WIRE MODE
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
AVDD, PVDD = 5V,DVDD = 3.3V, AGND, PGND,DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK and ADCMCLK = 256fs unless
otherwise stated
PARAMETER SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
526
kHz
SCLK Low Pulse-Width
t
1
1.3
us
SCLK High Pulse-Width
t
2
600
ns
Hold Time (Start Condition)
t
3
600
ns
Setup Time (Start Condition)
t
4
600
ns
Data Setup Time
t
5
100
ns
SDIN, SCLK Rise Time
t
6
300
ns
SDIN, SCLK Fall Time
t
7
300
ns
Setup Time (Stop Condition)
t
8
600
ns
Data Hold Time
t
9
900
ns
SCLK glitch suppression
t
ps
0
5
ns
Table 7 2-Wire Control Interface Timing Information
t
3
t
1
t
6
t
9
t
2
t
5
t
7
t
3
t
4
t
8
SDIN
SCLK
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