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Wolfson WM8580, Инструкция по эксплуатации

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WM8580

 

 Production 

Data

 

w 

PD, Rev 4.7, March 2009

 

 

56

 

 

PLL CONFIGURATION 

The PLLs perform a configurable frequency multiplication of the input clock signal (f

1

). The 

multiplication factor of the PLL (denoted by ‘R’) is variable and is defined by the relationship: R = (f

2

 ÷ 

f

1

).  

The multiplication factor for each PLL is set using register bits PLLx_N and PLLx_K (refer to Table 
47). The multiplication effect of both the N and K multipliers are additive (i.e. if N is configured to 
provide a multiplication factor of 8 and K is configured to provide a multiplication factor of 0.192, the 
overall multiplication factor is 8 + 0.192 = 8.192). 

In order to choose and configure the correct values for PLLx_N and PLLx_K, multiplication factor R 
must first be calculated. Once value R is calculated, the value of PLLx_N is the integer (whole 
number) value of R, ignoring all digits to the right of the decimal point. For example, if R is calculated 
to be 8.196523, PLL_N is simply 8. 

Once PLLx_N is calculated, the PLLx_K value is simply the integer value of (2

22

 (R-PLLx_N)). For 

example, if R is 8.196523 and PLLx_N is 8, PLLx_K is therefore (2

22

 (8.196523-8)), which is 824277 

(ignoring all digits to the right of the decimal point). 

Note:

  

The PLLs are designed to operate with best performance (shortest lock time and optimum stability) 
when f

2 

is between 90 and 100MHz and PLLx_N is 8. However, acceptable PLLx_N values lie in the 

range 5 

≤

 PLLx_N 

≤

 13. 

Each PLL has an output divider to allow the f

2

 clock signal to be divided to a frequency suitable for 

use as the source for the MCLK and CLKOUT outputs, the S/PDIF transmitter and the internal ADC 
and DACs. The divider output is configurable and is set by the FREQMODE_A or FREQMODE_B 
bits in conjunction with the POSTSCALE_A and POSTSCALE_B bits. Each PLL is also equipped 
with a pre-scale divider which offers frequency divide by one or two before the OSCCLK signal is 
input into the PLL. Please refer to Table 49 for details. 

REGISTER 

ADDRESS 

BIT LABEL  DEFAULT 

DESCRIPTION 

R3 

PLLA 4 

03h 

0 PRESCALE_A 

0 

R7 

PLLB 4 

07h 

0 PRESCALE_B 

0 

PLL Pre-scale Divider Select 
0 = Divide by 1 (PLL input clock = 
oscillator clock) 
1 = Divide by 2 (PLL input clock = 
oscillator clock 

÷

 2) 

Note: PRESCALE_A must be set to 
the same value as PRESCALE_B in 
PLL S/PDIF receiver mode. 

R3 

PLLA 4 

03h 

4:3 FREQMODE_A 

[1:0] 

 

10 

 

R7 

PLLB 4 

07h 

4:3 FREQMODE_B 

[1:0] 

10 

PLL Output Divider Select 
PLL S/PDIF Receiver Mode 
FREQMODE_A is automatically 
controlled. FREQMODE_B is not 
used. 
PLL User Mode 
Used in conjunction with the 
POSTSCALE_x bits. Refer to Table 
50. 

R3 

PLLA 4 

03h 

1 POSTSCALE_A 

0 

R7 

PLLB 4 

07h 

1 POSTSCALE_B 

0 

PLL Post-scale Divider Select 
PLL S/PDIF Receiver Mode 
POSTSCALE_A is used to configure 
a 256fs or 128fs PLLACLK, 
POSTSCALE_B is not used. Refer 
to Table 51. 
PLL User Mode 
Used in conjunction with the 
FREQMODE_x bits. Refer to Table 
50. 

Table 49  Pre and Post PLL Clock Divider Control 

Downloaded from 

Elcodis.com

 

electronic components distributor

 

Содержание WM8580

Страница 1: ...figuration is also supported The device has two PLLs that can be configured independently to generate two system clocks for internal or external use Device control and setup is via a 2 wire or 3 wire...

Страница 2: ...WM8580 Production Data w PD Rev 4 7 March 2009 2 BLOCK DIAGRAM Downloaded from Elcodis com electronic components distributor...

Страница 3: ...17 CONTROL INTERFACE OPERATION 18 DIGITAL AUDIO INTERFACES 22 AUDIO DATA FORMATS 24 AUDIO INTERFACE CONTROL 28 DAC FEATURES 30 ADC FEATURES 39 DIGITAL ROUTING OPTIONS 40 CLOCK SELECTION 42 PHASE LOCK...

Страница 4: ...EMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8580AGEFT V 40 to 85o C 48 lead TQFP Pb free MSL2 260 C WM8580AGEFT RV 40 to 85o C 48 lead TQFP Pb free tape and reel M...

Страница 5: ...dio Interface PAIF receiver left right word clock 23 PAIFRX_BCLK Digital Input Output Primary Audio Interface PAIF receiver bit clock 24 MCLK Digital Input Output System Master clock 256 384 512 768 1...

Страница 6: ...function shown in column 2 Otherwise the GPOnOP registers determine the MFP function as shown in columns 3 and 4 PIN NAME HARDWARE CONTROL MODE FUNCTION 1 SECONDARY AUDIO INTERFACE FUNCTION 2 S PDIF...

Страница 7: ...Audio Interface SAIF Receiver data input SAIF_DOUT Digital Output Secondary Audio Interface SAIF Transmitter data output SAIF_BCLK Digital Input Output Secondary Audio Interface SAIF Bit Clock SAIF_LR...

Страница 8: ...hich has an unlimited floor life at 30o C 85 Relative Humidity and therefore will not be supplied in moisture barrier bags CONDITION MIN MAX Digital supply voltage 0 3V 3 63V Analogue supply voltage 0...

Страница 9: ...N TYP MAX UNIT DAC Performance Load 10k 50pF WM8580AGEFT V WM8580AGEFT RV 25 C 0dBFs Full scale output voltage 6 1 0 x VREFP 5 6 Vrms A weighted fs 48kHz 95 103 dB Unweighted fs 48kHz 100 dB A weighte...

Страница 10: ...97 dB Unweighted fs 96kHz 94 dB A weighted fs 96kHz AVDD 3 3V 94 dB A weighted fs 192kHz 97 dB Unweighted fs 192kHz 94 dB Signal to Noise Ratio See Terminology 1 2 4 SNR A weighted fs 192kHz AVDD 3 3V...

Страница 11: ...level VXIL 0 557 mV Input XTI HIGH level VXIH 853 mV Input XTI capacitance CXJ 3 32 4 491 pF Input XTI leakage IXleak 28 92 38 96 mA Output XTO LOW VXOL 15pF load capacitors 86 278 mV Output XTO HIGH...

Страница 12: ...e audio band 5 Channel Separation dB Also known as Cross Talk This is a measure of the amount one channel is isolated from the other Normally measured by sending a full scale signal down one channel a...

Страница 13: ...K 256fs unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information PAIFTX_LRCLK PAIFRX_LRCLK SAIF_LRCLK propagation delay from PAIFTX_BCLK PAIFRX_BCL...

Страница 14: ...SAIF_BCLK cycle time tBCY 50 ns PAIFTX_BCLK PAIFRX_BCLK SAIF_BCLK pulse width high tBCH 20 ns PAIFTX_BCLK PAIFRX_BCLK SAIF_BCLK pulse width low tBCL 20 ns PAIFTX_LRCLK PAIFRX_LRCLK SAIF_BCLK set up ti...

Страница 15: ...to CSB rising edge tSCS 60 ns SCLK pulse cycle time tSCY 80 ns SCLK duty cycle 40 60 60 40 ns SDIN to SCLK set up time tDSU 20 ns SDIN hold time from SCLK rising edge tDHO 20 ns SDO propagation delay...

Страница 16: ...Input Information SCLK Frequency 0 526 kHz SCLK Low Pulse Width t1 1 3 us SCLK High Pulse Width t2 600 ns Hold Time Start Condition t3 600 ns Setup Time Start Condition t4 600 ns Data Setup Time t5 1...

Страница 17: ...256fs 384fs 512fs 768fs or 1152fs is provided In Slave mode selection between clock rates is automatically controlled In master mode the master clock to sample rate ratio is set by register control Sa...

Страница 18: ...L MODE WITH READ BACK REGISTER WRITE SDIN is used to program data SCLK is used to clock in the program data and CSB is used to latch the program data SDIN is sampled on the rising edge of SCLK The 3 w...

Страница 19: ...hannel Status Register 3 100 Channel Status Register 4 101 Channel Status Register 5 110 S PDIF Status Register 3 CONTREAD 0 Continuous Read Enable 0 Continuous read back mode disabled 1 Continuous re...

Страница 20: ...correct address the controller sends the first byte of control data REGA 6 0 i e the WM8580 register address plus the first bit of register data The WM8580 then acknowledges the first data byte by pul...

Страница 21: ...using the protocol shown in Figure 10 Figure 10 2 Wire Continuous Readback If CONTREAD is set to zero the user can read back directly from the register by writing to the register address to which the...

Страница 22: ...require both a left right clock LRCLK and a bit clock BCLK These can be supplied externally slave mode or they can be generated internally master mode When in master mode the BCLKs and LRCLKs for an i...

Страница 23: ...8kHz 6 144 9 216 12 288 18 432 24 576 36 864 Unavailable 88 2kHz 11 2896 16 9344 22 5792 33 8688 Unavailable Unavailable Unavailable 96kHz 12 288 18 432 24 576 36 864 Unavailable Unavailable Unavailab...

Страница 24: ...16 20 24 and 32 bits with the exception of 32 bit right justified mode which is not supported Audio Data for each stereo channel is time multiplexed with the interface s Left Right Clock LRCLK indica...

Страница 25: ...input data is sampled by the WM8580 on the first rising edge of BCLK following a LRCLK transition The MSB of the output data changes on the same falling edge of BCLK as LRCLK and may be sampled on the...

Страница 26: ...mples and high during the right samples Figure 16 I2 S Mode Timing Diagram DSP MODE A In DSP Mode A the MSB of Channel 1 left data is sampled on the second rising edge of BCLK following a LRCLK rising...

Страница 27: ...iming Diagram PAIF SAIF Transmitter Data DSP MODE B In DSP Mode B the MSB of Channel 1 left data is sampled on the first BCLK rising edge following a LRCLK rising edge Channel 1 right data then follow...

Страница 28: ...register bits e g PAIFRXBCP the polarity of BCLK may be reversed allowing input data and LRCLK to be sampled on the falling edge of BCLK Setting the bit clock polarity register for a transmit interfa...

Страница 29: ...SAIFWL 1 0 10 SAIF Audio Data Word Length 11 32 bits see Note 1 2 10 24 bits 01 20 bits 00 16 bits 4 SAIFLRP 0 In LJ RJ I 2 S modes 0 LRCLK not inverted 1 LRCLK inverted In DSP Format 0 DSP Mode A 1...

Страница 30: ...N 1 0 DAC1SEL 1 0 00 3 2 DAC2SEL 1 0 01 R15 DAC Control 1 0Fh 5 4 DAC3SEL 1 0 10 DAC digital input select 00 DAC takes data from DIN1 01 DAC takes data from DIN2 10 DAC takes data from DIN3 Table 17 D...

Страница 31: ...0 1001 1111 L R 2 L R 2 Table 19 DAC Attenuation Register PL ZERO FLAG OUTPUT Each DAC channel has a zero detect circuit which detects when 1024 consecutive zero samples have been input Should both ch...

Страница 32: ...tection circuit control and automute control 0 Infinite zero detect automute disabled 1 Infinite zero detect automute enabled Table 21 IZD Register With IZD enabled applying 1024 consecutive zero inpu...

Страница 33: ...gital Attenuation DACR 2 17h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 Store RDA2 in intermediate latch no change to output 1 Apply RDA2 and update attenuation on...

Страница 34: ...All DACs use attenuations as programmed 1 Right channel DACs use corresponding left DAC attenuations Table 24 DAC Attenuation Register DACATC The digital volume control also incorporates a zero cross...

Страница 35: ...23 The MUTE pin can also be used to apply soft mute to the DAC selected by the DZFM register bits However if the MPDENB register bit is set the MUTE pin will activate a soft mute for all DACs REGISTER...

Страница 36: ...tion Data w PD Rev 4 7 March 2009 36 Figure 23 Application and Release of Mute 2 5 2 1 5 1 0 5 0 0 5 1 1 5 0 0 001 0 002 0 003 0 004 0 005 0 006 Time s Downloaded from Elcodis com electronic component...

Страница 37: ...gital volume Volume register Decode Channel 1 Analogue Mute Channel 2 Analogue Mute Channel 3 Analogue Mute Channel 1 Softmute Channel 2 Softmute Channel 3 Softmute DAC_SRC 1 0 00 S PDIF Rx Data PCM_N...

Страница 38: ...de emphasis filter for DAC 1 DEEMP 1 enables the de emphasis filter for DAC 2 and DEEMP 2 enables the de emphasis filter for DAC 3 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 2 0 DEEMP 2 0 000 De e...

Страница 39: ...n at 96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit This changes the ADC signal processing oversampling rate from 128fs to 64fs Similarly for ADC operation at 192kHz i...

Страница 40: ...eceiver allow the data received on any DIN pin to be routed to any DAC Any DIN pin routed to DAC1 can also be routed to the S PDIF transmitter and Secondary Audio Interface Transmitter DAC1 may also b...

Страница 41: ...eived data 01 ADC digital output data 10 SAIF Receiver data R14 SAIF 2 0Eh 8 7 SAIFTX_SRC 1 0 00 Secondary Audio Interface Transmitter Source 00 S PDIF received data 01 ADC digital output data 11 PAIF...

Страница 42: ...multiplexer select bits to select TX_CLK generated based on TX_CLKSEL register bits and digital routing configuration TX_CLKSEL User programmed register select bits Reg8 bits 5 4 to select TX_CLK PAI...

Страница 43: ...ACE The DACs are driven from an internal clock called the DAC_CLK The DAC_CLKSEL bits reg8 bits 1 0 select a clock to drive the DAC and the possible sources of DAC_CLK are MCLK PLLACLK or PLLBCLK The...

Страница 44: ...ator needs to use a common LRCLK In this case the PAIFRX_LRCLK should be used This is done by setting register bit RX2DAC_MODE 1 allowing the PAIF_LRCLK to be used to generate the sampling rate In thi...

Страница 45: ...which the ADC operates is determined by the ADC Rate module Which is part of the ADC The ADC rate module divides down the ADC_CLK and calculates the rate at which the ADC operates based on the ADC_CLK...

Страница 46: ...00 ADCMCLK pin 01 PLLACLK 10 PLLBCLK 11 MCLK pin R29 ADC Control 1 1Dh 7 5 ADCRATE 2 0 010 ADC Rate Control only used when the S PDIF Transmitter is the only interface sourcing the ADC 000 128fs 001...

Страница 47: ...ter operates is determined by the S PDIF transmitter rate module which is part of the S PDIF Tx interface The transmitter rate module calculates the rate based on the digital routing setup Table 38 su...

Страница 48: ...LK and the PAIFRX_LRCLK pins In master mode the BCLK and LRCLK driving the PAIF Rx are generated by the Master Mode Clock Gen module The control of this module is described on page 22 The clock suppli...

Страница 49: ...s automatic and is based on the digital routing configuration Figure 30 illustrates the clock configuration and Table 41 gives some examples of clock routing based on digital routing configuration Fig...

Страница 50: ...lected and it is recommended that the interface operate in master mode However if the SAIF Transmitter sources something other than the S PDIF Receiver and the S PDIF Receiver is powered up then the P...

Страница 51: ...the relevant CLK_SEL register Figure 32 to Figure 37 illustrate this over ride capability REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R8 CLKSEL 08h 6 CLKSEL_MAN 0 Clock selection auto configuratio...

Страница 52: ...ta w PD Rev 4 7 March 2009 52 Figure 35 Manual Clock Over ride of PAIF Tx Figure 36 Manual Clock Over ride of PAIF Rx Figure 37 Manual Clock Over ride of SAIF Downloaded from Elcodis com electronic co...

Страница 53: ...led Whenever the PLLs or the S PDIF receiver is enabled the OSCCLK signal must be present to enable the PLLs to generate the necessary clock signals The oscillator uses a Pierce type oscillator drive...

Страница 54: ...1 Power Down PLL Table 46 PLL Power Down Control The PLLs have two modes of operation PLL S PDIF Receive Mode Selected if S PDIF Receiver Enabled In S PDIF receive mode PLLA is automatically controll...

Страница 55: ...8 1101 Fractional K part of PLLB frequency ratio I Value K is one 22 digit binary number spread over registers R4 R5 and R6 as shown Note PLLB_K must be set to specific values when the S PDIF receiver...

Страница 56: ...x_N values lie in the range 5 PLLx_N 13 Each PLL has an output divider to allow the f2 clock signal to be divided to a frequency suitable for use as the source for the MCLK and CLKOUT outputs the S PD...

Страница 57: ...d FREQMODE_B 1 0 10 will configure the f2 to PLLBCLK divider as 8 and hence will set the f2 frequency at 98 304MHz this value is within the 90 to 100MHz range and is hence acceptable POSTSCALE_B 0 FRE...

Страница 58: ...s When considering settings not shown in this table the key configuration parameters which must be selected for optimum operation are 90MHz f2 100MHz 5 PLLx_N 13 OSCCLOCK 10 to 14 4MHz or 16 28 to 27M...

Страница 59: ...are configured by default to allow S PDIF receiver operation using a 12MHz crystal clock The appropriate PLLB register values must be updated if any crystal clock frequency other than 12MHz is used R...

Страница 60: ...flags and clocks An IEC 60958 3 compatible S PDIF transceiver is integrated into the WM8580 Operation of the S PDIF function may be synchronous or asynchronous to the rest of the digital audio circui...

Страница 61: ...tatus data using data read from S PDIF transmitter channel status register 0 Channel data equal to recovered channel data 1 Channel data taken from channel status registers 3 REAL_ THROUGH 0 S PDIF Th...

Страница 62: ...k can be configured by setting the Channel Status Bit Control registers see Table 56 to Table 60 If TXSRC 00 S PDIF receiver the Channel Status bits are transmitted with the same values recovered by t...

Страница 63: ...4 CHNUM1 1 0 00 11 Do not use channel number Channel Number for Subframe 2 CHNUM2 Function 00 Do not use channel number 01 Send to Left Channel 10 Send to Right Channel R33 SPDTXCHAN 3 21h 7 6 CHNUM2...

Страница 64: ...e S PDIF specification for details 0000 original sampling frequency not indicated Table 60 S PDIF Transmitter Channel Status Bit Control 5 S PDIF RECEIVER INPUT SELECTOR The S PDIF receiver has one de...

Страница 65: ...The S PDIF Rx interface ALWAYS receives 24 bits but if the actual length of the audio data sample indicated by MAXWL and RXWL is less than 24 bits then the user has the option to truncate these 24 bit...

Страница 66: ...d stored in registers the Channel Status Update CSUD bit is set to indicate that the status registers have updated and are ready for readback After readback CSUD are cleared until the registers are ne...

Страница 67: ...3 for details R47 SPDRXCHAN 4 2Fh read only 5 4 CLKACU 1 0 29 28 Clock Accuracy of received clock 00 Level II 01 Level I 10 Level III 11 Interface frame rate not matched to sampling frequency Table 65...

Страница 68: ...been detected 0 Sync code not detected 1 Sync code detected received data is not audio PCM S PDIF Status Register CPY_N Recovered Channel Status bit 2 active low 0 Copyright is asserted for this data...

Страница 69: ...egister can be read to reveal the satus of the flag See Table 69 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 UPD_UNLOCK UNLOCK flag update signal 0 INT_N not caused by update to UNLOCK flag 1 INT...

Страница 70: ...the input S PDIF signal is not present 0 Locked onto incoming S PDIF stream 1 Not locked to the incoming S PDIF stream or the incoming S PDIF stream is not present Table 69 S PDIF Status Register The...

Страница 71: ...pted via the INT_N signal leaving the WM8580 to handle the error condition If the TRANS_ERR and INVALID error flags are masked using the MASK register the WM8580 output data from the S PDIF Rx interfa...

Страница 72: ...automatically muted using the soft mute feature As described above any change of AUDIO_N or PCM_N status will cause an INT_N interrupt UPD_NON_AUDIO to be generated If the MASK register bit for AUDIO_...

Страница 73: ...itter is powered down by setting SPDIFTXD Setting SPDIFRXD powers down the S PDIF receiver The PLL Oscillator and S PDIF clock recovery circuits are powered down by setting PLLPD OSCPD and SPDIFPD res...

Страница 74: ...3 0 0 DACs under control of DACPD 3 0 1 All DACs are disabled 0 OSCPD 0 OSC output powerdown 0 OSC output enabled 1 OSC output disabled A CMOS input can be applied to the OSC input when powered down 1...

Страница 75: ...present to operate PORB is asserted low until AVDD DVDD and VMID voltages have risen above their reset thresholds When these three conditions have been met PORB is released high When PORB is released...

Страница 76: ...Vpora 0 5 0 7 1 0 V Vporr 0 5 0 7 1 1 V Vpora_off 1 0 1 4 2 0 V Vpord_off 0 6 0 8 1 0 V Table 74 Typical POR Operation In a real application the designer is unlikely to have control of the relative po...

Страница 77: ...LABEL DEFAULT DESCRIPTION R29 ADC CONTROL 1 1Dh 8 VMIDSEL 1 VMID Impedance Selection 0 High impedance power saving 1 Low impedance fast power on DEVICE ID READBACK Reading from registers R0 R1 and R2...

Страница 78: ...ame 1 Sub frame A 0 Sub frame B MFP10 192BLK Indicates start of 192 frame block High for duration of frame 0 low after frame 0 Table 78 Hardware Mode Status Pins DIGITAL AUDIO INTERFACE CONTROL In Har...

Страница 79: ...e overwritten parity and bi phase errors have will not cause data to be overwritten POWERDOWN CONTROL In Software Control Mode the chip is powered down by default In Hardware Control Mode the chip is...

Страница 80: ...FTX_BCLK and the PAIF_LRCLK If the PAIF or DACs source the S PDIF Rx interface then the PAIFTX_BCLK and the PAIF_LRCLK input clocks must be synchronous to clock driving the S PDIF interface If these c...

Страница 81: ...FTXLRP PAIFTXWL 1 0 PAIFTXFMT 1 0 010001010 R14 SAIF 2 0E SAIFTX_SRC 1 0 SAIF_EN SAIFBCP SAIFLRP SAIFWL 1 0 SAIFFMT 1 0 000001010 R15 DAC CONTROL 1 0F RX2 DAC_M ODE 0 0 DAC3SEL 1 0 DAC2SEL 1 0 DAC1SEL...

Страница 82: ...actional K part of PLLA frequency rIio R Value K is one 22 digit binary number spread over registers R0 R1 and R2 as shown Reading from these registers will return the device ID R0 returns 10000000 80...

Страница 83: ...PRESCALE_A must be set to the same value as PRESCALE_B in PLL S PDIF receiver mode 1 POSTSCALE_B 0 PLL Post scale Divider Select PLL S PDIF Receiver Mode POSTSCALE_A is used to configure a 256fs or 12...

Страница 84: ...aster Mode BCLK Rate 00 64 BCLKs per LRCLK 01 32 BCLKs per LRCLK 10 16 BCLKs per LRCLK 11 BCLK System Clock 5 PAIFRXMS 0 PAIF Receiver Master Slave Mode Select 0 Slave Mode 1 Master Mode R9 PAIF 1 09h...

Страница 85: ...FMT 1 0 10 PAIF Receiver Audio Data Format Select 11 DSP Format 10 I2 S Format 01 Left justified 00 Right justified 3 2 PAIFRXWL 1 0 10 PAIF Receiver Audio Data Word Length 11 32 bits see Note 10 24 b...

Страница 86: ...y Audio Interface Transmitter Source 00 S PDIF received data 01 ADC digital output data 10 SAIF Receiver data 1 0 SAIFFMT 1 0 10 SAIF Audio Data Format Select 11 DSP Format 10 I2 S Format 01 Left just...

Страница 87: ...10 Right Left 0111 L R 2 Left 1000 Mute Right 1001 Left Right 1010 Right Right 1011 L R 2 Right 1100 Mute L R 2 1101 Left L R 2 1110 Right L R 2 3 0 PL 3 0 1001 1111 L R 2 L R 2 6 4 DZFM 2 0 000 Selec...

Страница 88: ...pply LDA1 and update attenuation on all channels 7 0 RDA1 6 0 11111111 0dB Digital Attenuation control for DAC1 Right Channel DACR1 in 0 5dB steps See Table 23 R21 Digital Attenuation DACR 1 15h 8 UPD...

Страница 89: ...ed when the S PDIF Transmitter is the only interface sourcing the ADC 000 128fs 001 192fs 010 256fs 011 384fs 100 512fs 101 768fs 110 1152fs R29 ADC Control 1 1Dh 8 VMIDSEL 1 VMID Impedance Selection...

Страница 90: ...Code Refer to S PDIF specification for details 00h indicates general mode 3 0 SRCNUM 3 0 0000 Indicates S PDIF source number No definitions are attached to data Channel Number for Subframe 1 CHNUM1 C...

Страница 91: ...ion Mask 0 disabled data word is truncated as described in Table 66 1 enabled data word is not truncated R37 INTMASK 25h 8 0 MASK 8 0 000000000 When a flag is masked it does not update the Error Regis...

Страница 92: ...R39 GPO2 27h 8 ALWAYSVALID 0 Automatic Error Handling Configuration for INVALID Flag 0 INVALID flag automatic error handling enabled 1 INVALID flag automatic error handling disabled 3 0 GPO5OP 3 0 01...

Страница 93: ...entification 0 Data word represents audio PCM samples 1 Data word does not represent audio PCM samples 2 CPY_N 0 Copyright is asserted for this data 1 Copyright is not asserted for this data 3 DEEMPH...

Страница 94: ...t non audio code defined in IEC 61937 has been detected 0 Sync code not detected 1 Sync code detected received data is not audio PCM 2 CPY_N Recovered Channel Status bit 2 0 Copyright is asserted for...

Страница 95: ...1 S PDIF Transmitter disabled R51 PWRDN 2 33h 5 SPDIFRXD 1 S PDIF Receiver powerdown 0 S PDIF Receiver enabled 1 S PDIF Receiver disabled 2 0 READMUX 2 0 000 Determines which status register is to be...

Страница 96: ...dB 0 0 4535fs Passband 6dB 0 5fs Passband ripple 0 01 dB Stopband 0 5465fs Stopband Attenuation f 0 5465fs 65 dB DAC Filter 0 05 dB 0 444fs Passband 3dB 0 487fs Passband ripple 0 05 dB Stopband 0 555f...

Страница 97: ...ncy Fs Figure 43 DAC Digital Filter Frequency Response 44 1 48 and 96kHz Figure 44 DAC Digital Filter Ripple 44 1 48 and 96kHz 80 60 40 20 0 0 0 2 0 4 0 6 0 8 1 Response dB Frequency Fs 1 0 8 0 6 0 4...

Страница 98: ...ponse dB Frequency kHz 1 0 8 0 6 0 4 0 2 0 0 2 0 4 0 6 0 8 1 0 5 10 15 20 Response dB Frequency kHz Figure 49 De Emphasis Frequency Response 48kHz Figure 50 De Emphasis Error 48kHz ADC FILTER RESPONSE...

Страница 99: ...digital high pass filter to remove DC offsets The filter response is characterised by the following polynomial Figure 53 ADC Highpass Filter Response 1 z 1 1 0 9995z 1 H z 15 10 5 0 0 0 0005 0 001 0...

Страница 100: ...Production Data w PD Rev 4 7 March 2009 100 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 54 Recommended External Components Downloaded from Elcodis com electronic components distri...

Страница 101: ...Production Data WM8580 w PD Rev 4 7 March 2009 101 Figure 55 Recommended External Components Downloaded from Elcodis com electronic components distributor...

Страница 102: ...TION ABC REFER TO THIS SPECIFICATION FOR FURTHER DETAILS DM004 C FT 48 PIN TQFP 7 x 7 x 1 0 mm Symbols Dimensions mm MIN NOM MAX A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 b 0 17 0 22 0 27 c 0 09 0 20 D 9...

Страница 103: ...s by the customer for such purposes is at the customer s own risk Wolfson does not grant any licence express or implied under any patent right copyright mask work right or other intellectual property...

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