110502
PRODUCT MANUAL EPX-C380
75
APPENDIX - B
POST CODES
If the system hangs before the BIOS can process the error, the value displayed at the I/O port I/O address 80h is the last
test that performed. In this case, the screen does not display an error code.
The following is a list of the checkpoint codes written at the start of each test and their corresponding audio beep codes
issued for terminal errors.
Code
Beeps
Location
Description
01h
IPMI initialization
02h
Verify real mode
03h
Disable non-maskable interrupt (NMI)
04h
Get CPU type
06h
Hardware initialization
07h
Chipset BIOS deshadow
08h
Chipset initialization
09h
Set IN POST flag
0Ah
CPU initialization
0Bh
CPU cache on
0Ch
Cache initialization
0Eh
I/O initialization
0Fh
FDISK initialization
10h
Power management initialization
11h
Register initialization
12h
Restore CR0
13h
PCI bus master reset
14h
8742 initialization (keyboard/embedded controller)
16h
1-2-2-3
Checksum BIOS ROM
17h
Pre-size RAM (initialize cache before memory auto size)
18h
Timer initialization (8254 CTC)
1Ah
DMA initialization (8237 DMAC)
1Ch
Reset PIC (8259 PIC)
20h
1-3-1-1
Test DRAM refresh
22h
1-3-1-3
Test 8742 Keyboard Controller
24h
Set huge ES (segment register to 4 GB)
26h
Enable A20
28h
Auto size DRAM
29h
POST memory manager (PMM) initialization
2Ah
Zero base (clear 512 KB base RAM)
2Bh
Enhanced CMOS initialization
2Ch
1-3-4-1
Address test (RAM failure
on address line
xxxx
*)
2Eh
1-3-4-3
Base RAM Low (RAM failure
on data bits
xxxx
* of low
byte)
2Fh
Pre-sys shadow (Enable cache before system BIOS shadow)
30h
Base RAM High (RAM failure on data bits
xxxx
* of high byte)
32h
Compute speed (test CPU bus-clock frequency)
33h
Post Dispatch Manager (PDM) initialization
34h
CMOS test
35h
Register re-initialization
36h
Check shutdown (perform warm restart)
Preliminary