110502
PRODUCT MANUAL EPX-C380
32
This read/write register is the primary window to the memory array. A value written to this port will be written to the address
in the memory array specified by the MSB register, the NSB register, and the current LSB counter address. In like fashion, a
read from this I/O address will result in the current memory array data at the address specified by the MSB register, the NSB
reigster, and the LSB address counter. In either case, read or write, an access to this register results in the LSB address
counter being incremented immediately following the access so that the next access will be at the next sequential address in
the array. This incrementing process does
not
carry into the NSB or MSB register which must be rewritten every 256 bytes.
This read/write register is used to access the memory array when post incrementing of the LSB counter is not desired.
The byte written or read will still be specified by the 24-bit combination of the MSB register, the NSB register, and the LSB
counter. However, the LSB counter will
not
be altered following the access. It will then be necessary to do one more read
from Data Access Register A in order to bump the address to the next byte.
This write-only register controls the write protect function of the 1 MB SRAM board. On power up, the write protect bit is
cleared (disabling writes) and must be explicitly enabled by writing a
1
to the I/O port at the BASE a4. To re-enable
the write protection, write a
0
at this register. The
USSD.SYS
device will enable writing only during that time when a sector
is being transferred, which contributes greatly to data safety and integrity.
OFFSET 3 - Data Access Register B
D7 - D7 of memory data
D6 - D6 of memory data
D5 - D5 of memory data
D4 - D4 of memory data
D3 - D3 of memory data
D2 - D2 of memory data
D1 - D1 of memory data
D0 - D0 of memory data
OFFSET 4 - Write Protect Register
D7 - D6 - Reserved
D0 - Write Protect Bit, 0 = Protected, 1 = Writeable
Preliminary
