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PRODUCT MANUAL EPX-C380
31
1 MB SRAM
(Battery-Backed User Data Space)
Visual
Index
The EPX-C380 board provides 1 MB of battery-backed user SRAM.
There are four I/O registers used for accessing the memory array. The register definition and usage is defined below.
This register is write-only and holds the upper 8 bits of the 24-bit address used to access the 1 MB SRAM.
This register is write-only and holds the middle 8 bits of address used to access the 1 MB memory array. Writing this
register also clears the LSB address counter to 0.
OFFSET 0 - MSB Address Register
D7 - A23 of access address
D6 - A22 of access address
D5 - A21 of access address
D4 - A20 of access address
D3 - A19 of access address
D2 - A18 of access address
D1 - A17 of access address
D0 - A16 of access address
OFFSET 1 - NSB Address Register
D7 - A15 of access address
D6 - A14 of access address
D5 - A13 of access address
D4 - A12 of access address
D3 - A11 of access address
D2 - A10 of access address
D1 - A9 of access address
D0 - A8 of access address
OFFSET 2 - Data Access Register A
D7 - D7 of memory data
D6 - D6 of memory data
D5 - D5 of memory data
D4 - D4 of memory data
D3 - D3 of memory data
D2 - D2 of memory data
D1 - D1 of memory data
D0 - D0 of memory data
NOTE: SRAM is not applicable for model EPX-C380-S1-0.
Preliminary
