Chapter - 2
Hardware Description
Clock Generator:
All the necessary clock rates such as Frame Sync, Bit Clock and the 256KHz for the
W6810DK evaluation system are driven from a single 4.096MHz crystal oscillator.
Frame Sync:
The Frame Sync is generated on the W6810DK evaluation board. J19 and J20(SW5)
control the FSR (Frame Sync Receive) and FSX (Frame Sync Transmit) routing.
Populating these jumpers also routes the signal to the 40-pin header (J11).
Setting Dip Switches
:
Switch SW2 selects the width of the Frame Sync. The pulse width is set as a number of
BCLKs. The following number of BCLKs for Frame Sync can be set with SW2.
•
1-2-3-4-5-6-7-8
The Dip-Switch SW2 configurations are:
Frame Sync = 8 BCLK
Frame Sync = 7 BCLK
ON
8
Frame Sync = 6 BCLK
1
ON
OFF
OFF
Frame Sync = 5 BCLK
ON
ON
OFF
OFF
WECA W6810DK
2727 N First Street, San Jose CA 95134
5
