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WAGO-SPEEDWAY 767
Counter Function
89
767-5201 TTL Incremental/SSI Encoder
Manual
Version 1.1.0
9.2.3
Example for Controlling Two Counters via Process Data
Example 1: Preparation for the Latch Signal
Table 53: Example: Preparation for the latch signal
Binary [bit 15…0]
Hexadeci
mal
Description:
0xxx xxxx xxxx xxx1
Latch unlocked
Read cyclic status register until bit 0 = 1, then
001x xxxx xxxx xxxx
Select latch value for the process image
Example 2: Set Counter Value as Default
Table 54: Example: Set counter value as default
Binary [bit 15…0]
Hexadeci
mal
Description:
00xx xxxx xxxx xxxx
Output status
xxx1 0010 xxxx xxxx
Apply default value as counter value
00xx xxxx xxxx xxxx
Output status
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