VXI VT1422A, Руководство пользователя

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Programming the VT1422A for Data Acquisition and Control 145 Chapter 4
Enabling Events to
be Reported in the
Status Byte
There are two sets of registers that individual status conditions must pass
through before that condition can be reported in the instrument’s Status
Byte. These are the Transition Filter Registers and the Enable registers.
They provide selectivity in recording and reporting module status conditions.
Configuring the
Transition Filters
Figure 4-10 shows that the Condition Register outputs are routed to the
input of the Negative Transition and Positive Transition Filter Registers.
For space reasons they are shown together but are controlled by individual
SCPI commands. It is important to understand that whether an event from
the Condition Register was negative-going (NTR bit 1) or positive-going
(PTR bit 1), the Event Register always records the event by setting a bit
to 1. The only way Event Register Bits are changed from 1 to 0 is with the
STAT:...:EVENt?, STAT:PRESet, *CLS, or *RST commands. Here is the
truth table for the Transition Filter Registers:
The Power-on default condition is: All Positive Transition Filter Register
bits set to one and all Negative Transition Filter Register bits set to 0.
This applies to both the Operation and Questionable Data Groups.
An Example using the Operation Group
Suppose that having the module report via the Status System when it has
completed executing *CAL? is desired. The "Calibrating" bit (bit 0) in the
Operation Condition Register goes to 1 when *CAL? is executing and
returns to 0 when *CAL? is complete. In order to record only the negative
transition of this bit in the STAT:OPER:EVEN register, send:
STAT:OPER:PTR 32766
All ones in Pos Trans Filter
register except bit 0=0
STAT:OPER:NTR 1
All zeros in Neg Trans Filter
register except bit 0=1
Now, when *CAL? completes and Operation Condition Register bit zero
goes from 1 to 0, Operation Event Register bit zero will become a 1.
Condition Reg Bit PTRansition Reg Bit NTRansition Reg Bit Event Reg Bit
0
→
1
0 0 no change
1
→
0
0 0 no change
0
→
1
1 0 1
1
→
0
1 0 no change
0
→
1
0 1 no change
1
→
0
0 1 1
0
→
1
1 1 1
1
→
0
1 1 1