42: Configuring Terminal Server
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© Virtual Access 2018
GW1000 Series User Manual
Issue: 2.3
Page 449 of 463
Web: Synchronous mode
UCI: tservd.@port[0].sync mode
Opt: sync mode
Defines synchronous frame mode. This setting is only displayed if
an Atmel USB serial card is enabled.
hdlc
HDLC frame mode.
transp
Transparent mode.
Web: Use CRC32
UCI: tservd.@port[0].sync_crc32
Opt: sync_crc32
Defines whether to use CRC32 or CRC16 in HDLC mode. This
setting is only displayed if an Atmel USB serial card is enabled.
0
Use CRC16.
1
Use CRC32.
Web: DTR control mode
UCI: tservd.@port[0].dtr_control_mode
Opt: dtr_control_mode
Defines DTR line control modes. This setting is only displayed if
an Atmel USB serial card is enabled and port mode is X21.
auto
DTR set to on when port is open. Off when the
port is closed.
on
DTR always on.
off
DTR always off.
app
DTR controlled by the application.
ontx
In HDLC mode DTR is on during frame
transmission.
Web: RTS control mode
UCI: tservd.@port[0].rts_control_mode
Opt: rts_control_mode
Defines RTS line control modes. Only displayed if Atmel USB
serial card is enabled and port mode is X21.
auto
RTS set to on when port is open. Off when the
port is closed.
on
RTS always on.
off
RTS always off.
app
RTS controlled by the application.
ontx
In HDLC mode RTS is on during frame
transmission.
Web: Synchronous rate
UCI: tservd.@port[0].sync_speed
Opt: sync_speed
Defines the synchronous speed in bps. Set to 0 for external
clock. If not set to 0, an internal clock is used. This setting is
only displayed if an Atmel USB serial card is enabled.
64000
64 kbps
Range
2048000; 1024000; 768000; 512000; 384000;
256000; 128000; 19200; 9600
Web: Invert receive clock
UCI: tservd.@port[0].sync_invert_rxclk
Opt: sync_invert_rxclk
Defines receive clock inversion. Normal clock data is sampled on
falling edge. Inverted clock data is sampled on rising edge. This
setting is only displayed if an Atmel USB serial card is enabled.
0
Normal.
1
Invert.
Web: Invert transmit clock
UCI: tservd.@port[0].sync_invert_txclk
Opt: sync_invert_txclk
Defines transmit clock inversion. Normal clock data transmitted
on falling edge. Inverted clock data transmitted on rising edge.
Only displayed if Atmel USB serial card is enabled.
0
Normal.
1
Invert.
Web: RX MSBF
UCI: tservd.@port[0].sync_rx_msbf
Opt: sync_rx_msbf
Defines whether most significant bit is received first. This setting
is only displayed if an Atmel USB serial card is enabled.
0
Receive least significant bit first.
1
Receive most significant bit first.
Web: TX MSBF
UCI: tservd.@port[0].sync_tx_msbf
Opt: sync_tx_msbf
Defines whether most significant bit is transmitted first. This
setting is only displayed if an Atmel USB serial card is enabled.
0
Transmit least significant bit first.
1
Transmit most significant bit first.
Web: RX data delay
UCI: tservd.@port[0].sync_rxdata_dly
Opt: sync_rxdata_dly
Defines the number of bit positions to delay sampling data from
the detecting clock edge. This setting is only displayed if an
Atmel USB serial card is enabled.
0
Range