VIPA SSM-BG41, Руководство пользователя

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Manual BG41/BG42/BG43 Interface modules
Rev. 99/49 3-83
3.2.10.14 FB102 (UHR), operation of the internal clock
The clock situated on the interface building block can be set with the FB 102 (UHR) and sent to the
automation device. It is however possible to set the time automatically with the help of a DCF77
antenna module, which is available from VIPA.
For peripheral addressing please use a FB 103.
The following parameters are to be transferred with the loading of FB 102:
Des. Format Explanation
ADR KH Building blocks absolute base address
DB B Details of data block
FRG BI Release bit
NEUS M Block the building block
Tab. 3-17:List of parameters for the loading of FB102
ADR
(absolut) Input of the physical start address, under which the building block can be
accessed by the PLC. This start address can be set with the DIL switches S1 and
S2.
In the case of peripheral addressing enter the address, which you have set with the
DIL switch S1 on the building block, into FB103. The following addresses can be
loaded: BG41: PY128-PY252, BG42 and BG43: PY128-PY248.
DB Entry of the data blocks, in which the data record for setting the clock or the time
and date are filed (in delivery state DB 99). The following functions are carried
out in this data block:
Transfer time and date to PLC (BCD depiction)
Transfer time and date to PLC (ASCII character)
FRG If this bit is placed at 1, the date and time are read once or they are sent in order
to set the clock. After transmission the bit is returned to 0. If this bit is placed at 0
when loading FB 102, the building block will again leave immediately!
NEUS If the data handling block runs through with a set new start bit, the module will
be blocked for all SPS accesses. By loading the FB28 with a set new start bit, the
building block will be released again.