Viglen VIG520S, Руководство пользователя

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Integrated A.G.P. Compliant Target/66MHz Host-to-PCI Bridge
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AGP v2.0 Compliant
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Supports Additional AGP4X/2X interface and Fast Write Transaction
High throughout MuTIOL® Connect interfaced to SiS962 MuTIOL® Media I/O
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Bi-directional 16 bit data bus
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1 GB/s performance in 133MHz x 4 mode
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Distributed arbitration strategy with enhanced mode of contiguous DMA data streaming
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Packet based, pipelining, and split transaction scheme
Dedicated Isochronous Response Queue
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Built-in a high performance 256-bit 3D engine
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Built-in a high quality 3D engine
High Performance 2D Accelerator
LAN Subsystem
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Integrated Fast Ethernet controller and 10/100 megabit per second (Mbps)
Physical Layer Transceivers for the PCI local bus
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PCI specification revision 2.1 compliant
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32-bit glueless PCI host interface
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Plug and Play compatible
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Supports PCI clock frequency from DC to 33 MHz independent of network clock
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Supports network operation with PCI clock from 25Mhz to 33Mhz
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Supports both +3.3v and +5v PCI signalling
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High-performance 32-bit PCI bus master architecture with an integrated Direct
Memory Access (DMA ) Controller for low CPU and bus utilization
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Supports an unlimited PCI burst length
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Supports big endian and little endian byte alignments
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Supports PCI Device ID, Vendor ID/Subsystem ID, Subsystem Vendor ID
Programming through the EEPROM interface
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Implements optional PCI 3.3v auxiliary power source 3.3Vaux pin and optional
PCI power management event (PME#) pin
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IEEE 802.3 and 802.3u standard compatible
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IEEE 802.3u Auto Negotiation and Parallel detection for automatic speed
Selection
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Full duplex and half duplex mode for both 10 and 100 Mbps
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Fully compliant ANSI X3.263 TP-PMD physical sub-layer which includes adaptive
Equalization and Baseline Wander compensation
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Automatic Jam and IEEE 802.3x Auto-Negotiation for flow control
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Flexible hardware and software interrupt capability
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Single access to complete PHY register set
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Built-in waveform shaping requires no external filters
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Power down of 10Base-T/100Base-TX sections when not in use
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Jabber control and auto-polarity correction for 10Base-T.
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User programmable LED function mapping
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Supports software, enhanced software, and automatic polling schemes to internal PHY status
monitor and interrupt
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Supports 10BASE-T, 100BASE-TX, and any future
Supports PC97, PC98, and Net PC requirements
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Green PC compatible
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Supports Advanced Configuration and Power Interface Specification (ACPI) Revision 1.0