Vextrec GMB-486SPS, Руководство пользователя

Страница: 24 / 61

Hardware Configuration
19
2.4.2 CACHE SIZE AND MEMORY LOCATIONS
The table below describes the chip capacity and socket location required for each cache size
configuration. User can use 32Kx8-bit or 128Kx8-bit SRAM chips in banks 0 and 1, and in the Tag
RAM socket. Please note that; do not combine different chip capacities in banks 0 and 1.
Error!
Bookm
ark not
defined.
BANK 0 BANK 1 TAG
RAM
Cache
Size
U13 U14 U15 U16 U17 U18 U19 U20 U11
128K 32Kx8 32Kx8 32Kx8 32Kx8 NONE NONE NONE NONE 8Kx8
256K 32Kx8 32Kx8 32Kx8 32Kx8 32Kx8 32Kx8 32Kx8 32Kx8 16Kx8/
32Kx8
256K 64Kx8 64Kx8 64Kx8 64Kx8 NONE NONE NONE NONE 16Kx8/
32Kx8
512K 128Kx8 128Kx8 128Kx8 128Kx8 NONE NONE NONE NONE 32Kx8
1024K 128Kx8 128Kx8 128Kx8 128Kx8 128Kx8 128Kx8 128Kx8 128Kx8 64Kx8
Table 2: Cache Size Configuration
2.4.3 CACHE CHIP SOCKETS AND JUMPER LOCATIONS
The diagram below describes the location of the cache chip sockets and cache jumpers.
Fig 4 Cache Jumper and Socket Locatio