Multi-purpose I/O
EPM-31 Hardware Reference Manual
41
Table 9: J21 I/O Connector Pinout
J21 Pin
Signal
VL-CBR-2004B
Terminal Block
Terminal Block
Pin
1
Digital I/O 1
J1
5
2
Digital I/O 2
4
3
Digital I/O 3
3
4
Digital I/O 4
1
5
Ground
2
6
Digital I/O 5
J2
5
7
Digital I/O 6
4
8
Digital I/O 7
2
9
Digital I/O 8
1
10
Ground
3
11
Digital I/O 9
(Optional Timer Channel 5 output)
J3
5
12
Digital I/O 10
(Optional Timer Channel 5 output)
3
13
Digital I/O 11
(Optional Timer Channel 4 Gate input)
2
14
Digital I/O 12
(Optional Timer Channel 3 Gate input)
1
15
Ground
4
16
Digital I/O 13
(Optional Timer 3 output)
J4
4
17
Digital I/O 14
(Optional Timer 3 input)
3
18
Digital I/O 15
(Optional Timer 4 output)
2
19
Digital I/O 16
(Optional Timer 4 input)
1
20
Ground
5
FPGA registers control the mode on pins 11-14 and 16-19. By default, they are DIOs. There are
FPGA register settings to select the timer signals in 4-signal mode (pins 16-19) and 8-signal
mode (11-15 and 16-19).
DIO Guidelines
Consider the following guidelines when using the DIO lines.
V
OLTAGE
The DIO lines are 3.3 V Low-voltage TTL (LVTTL) compatible DIOs capable of
sourcing/sinking up to 4 mA of current. Level shifting or current limiting is necessary when
connecting signals with different voltage rails.
CAUTION:
Do not connect the DIO signals to ex5 V devices; doing so will damage the FPGA and
void the warranty.