Multi-purpose I/O
EPM-31 Hardware Reference Manual
38
User I/O Connector
The 40-pin J4 I/O connector incorporates the signals for the following:
Four USB ports
Eight GPIO lines (these are functionally muxed with six timer I/O signals per FPGA
registers). There are eight timer signals and they share digital I/Os 16-9. The eight GPIO
lines on the paddleboard each have an alternate mode, accessible using the FPGA’s
AUXMOD1 register. Refer to the
EPM-31 Programmer’s Reference Manual
for more
information on FPGA registers.
Three LEDs (two Ethernet link status LEDs and a programmable LED)
I
2
C clock and data signals
Push-button power switch
Push-button reset switch
Speaker output
This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
Figure 18 shows the location and pin orientation of the user I/O connector.
Figure 18. Location and Pin Orientation of User I/O Connector