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Interfaces and Connectors
EBX-18 Hardware Reference manual
44
Table 30: Digital I/O Connections – Channels 17-32
EBX-18 Board
J10 Pin
Signal CB-4004 Connector
11 Digital I/O 17
J3
Digital IO
(See Figure 23 on page
54)
12 Digital I/O 18
13 Digital I/O 19
14 Digital I/O 20
15 GND
16 Digital I/O 21
J4
Digital IO
(See Figure 23 on page
54)
17 Digital I/O 22
18 Digital I/O 23
19 Digital I/O 24
20 GND
21 Digital I/O 25
J6
Digital IO
(See Figure 23 on page
54)
22 Digital I/O 26
23 Digital I/O 27
24 Digital I/O 28
25 GND
26 Digital I/O 29
J7
Digital IO
(See Figure 23 on page
54)
27 Digital I/O 30
28 Digital I/O 31
29 Digital I/O 32
30 GND
D
IGITAL
I/O P
ORT
C
ONFIGURATION
For information on digital I/O port configuration refer to the EBX-18 Programmer’s Reference
Manual , (available on the EBX-18 Product Support Web Page ).
I
NTERRUPT
G
ENERATION
The EBX-18 digital I/O can be configured to issue hardware interrupts on the transition (high to
low or low to high) of any digital I/O pin. Note that this interrupt is shared among all SPI
devices on-board and externally connected to the EBX-18. Digital I/O port interrupt
configuration is achieved through I/O port register settings. Refer to the
Microchip MCP23S17
datasheet for more information.
The on-board digital I/O chips must be configured for open-drain and mirrored interrupts in order
for any SPI device to use hardware interrupts.