V VIZIO P42HDTV10A, Руководство по обслуживанию

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CONFIDENTIAL – DO NOT COPY Page 8- 54
File No. SG-0184
1. TMDS Digital Core
The core performs 10-to-8-bit TMDS decoding on the audio and video received from the three
TMDS differential data lines along with a TMDS differential clock. The TMDS core supports link
clock rates to 165MHZ, including CE modes to 720P/1080I/1080P.
2. Active port detection
The Pane Link core detects an active TMDS clock and actively toggling DE signal. These
states are accessible in register bits, useful for monitoring the status of the HDMI input or for
automatically powering down the receiver. The 5V supply from the HDMI connector is used as
a cable detect indicator. The sil9011 can monitor the presence of this+5V supply and, if and
when necessary, provide a fast audio mute without pops when it senses the HDMI cable pulled.
The microcontroller can also poll registers in the sil9011 to check whether an HDMI cable is
connected.
3. HDCP Decryption engine
The HDCP decryption engine contains all necessary logic to decrypt the incoming audio and
video data. The decryption process is entirely controlled by the host microprocessor through a
set sequence of register reads and wires through the DDC channel. Pre-programmed HDCP
keys and key Selection Vector are used in the decryption process. A resulting calculated to an
XOR mask during each clock cycle to decrypt the audio/video data in sync with the host.
4. Video Data Conversion and Video Output
The Sil9011 can output video in many different formats
as shown in the following figure.