SARA-R4 series - System Integration Manual
UBX-16029218 - R06
Design-in
Page 68 of 102
Additional considerations
If a 3.0 V Application Processor (DTE) is used, the voltage scaling from any 3.0 V output of the DTE to the
corresponding 1.8 V input of the module (DCE) can be implemented as an alternative low-cost solution, by
means of an appropriate voltage divider. Consider the value of the pull-up integrated at the input of the module
(DCE) for the correct selection of the voltage divider resistance values. Make sure that any DTE signal connected
to the module is tri-stated or set low when the module is in power-down mode and during the module power-
on sequence (at least until the activation of the
V_INT
supply output of the module), to avoid latch-up of circuits
and allow a proper boot of the module (see the remark below).
Moreover, the voltage scaling from any 1.8 V output of the cellular module (DCE) to the corresponding 3.0 V
input of the Application Processor (DTE) can be implemented by means of an appropriate low-cost non-inverting
buffer with open drain output. The non-inverting buffer should be supplied by the
V_INT
supply output of the
cellular module. Consider the value of the pull-up integrated at each input of the DTE (if any) and the baud rate
required by the application for the appropriate selection of the resistance value for the external pull-up biased by
the application processor supply rail.
Do not apply voltage to any UART interface pin before the switch-on of the UART supply source (
V_INT
),
to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to
the cellular module cannot be tri-stated or set low, insert a multi channel digital switch (e.g. TI
SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high
impedance before
V_INT
switch-on.
ESD sensitivity rating of UART interface pins is 1 kV (Human Body Model according to JESD22-A114).
Higher protection level could be required if the lines are externally accessible and it can be achieved by
mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to accessible points.
2.6.1.2
Guidelines for UART layout design
The UART serial interface requires the same consideration regarding electro-magnetic interference as any other
digital interface. Keep the traces short and avoid coupling with RF line or sensitive analog inputs, since the
signals can cause the radiation of some harmonics of the digital data frequency.
