TYAN Tomcat i945GM S3095, Руководство пользователя

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3.5 Advanced Chipset Features
In Advanced Chipset Features, you will be able to adjust many of the chipset
special features.
DRAM Timing Selectable
This option permits you to either manually select memory timings, or allow the
SPD (Serial Presence Detect) to determine the said timings automatically.
• Manual
•
By SPD
Note: On all memory timing settings, lower number is more aggressive.
CAS Latency Time
This setting controls the time delay (in clock cycles - CLKs) that passes before
the DRAM starts to carry out a read command after receiving it. This also
determines the number of CLKs for the completion of the first part of a burst
transfer. In other words, the lower the latency, the faster the transaction.
•
Auto
• 2
• 2.5
• 3
DRAM RAS# to CAS# Delay
This setting is the number of cycles from when a bank activate command is
issued until a read or write command is accepted, that is, before the CAS
becomes active.
•
Auto