TYAN Tomcat i945GM S3095, Руководство пользователя

Страница: 50 / 86

50
• 5
• 4
• 3
• 2
DRAM RAS# Precharge Time
This setting is the number of cycles needed to return data to its original location
to close the bank or number of cycles to page memory before the next bank
activate command can be issued.
•
Auto
• 5
• 4
• 3
• 2
Precharge Delay <tRAS>
This timing controls the length of the delay between the activation and
precharge commands -- basically how long after activation can the access cycle
be started again. This influences row activation time that is taken into account
when memory has hit the last column in a specific row, or when an entirely
different memory location is requested.
•
Auto
• 4 ~ 10
System Memory Frequency
Changing this option allows the memory to be run asynchronously from the FSB
but it is best if it is left at AUTO.
•
Auto
• DDR333
• DDR400
SLP_S4# Assertion Width
Set minimum assertion width of the SLP_S4# signal to ensure that the DRAM s
have been safely power-cycled.
•
4 to 5 sec.
• 3 to 4 sec.
• 2 to 3 sec.
• 1 to 2 sec.
Memory Hole at 15M-16M
Certain ISA cards require exclusive access to the 1MB block of memory, from
the 15th to the 16th megabyte, to work properly. This BIOS feature allows you
to reserve that 1MB block of memory for such cards to use.
If you
enable this feature, 1MB of memory ( the 15th MB ) will be reserved
exclusively for the ISA card's use. This effectively reduces the total amount of
memory available to the operating system by 1MB.
If you
disable this feature, the 15th MB of RAM will not be reserved for the ISA