TS-AVE3/B
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BIOS SETUP
3.5 Advanced Chipset Features
This option will change the values of the chipset registers and the system settings will alter. Do
not change any values if you are unfamiliar with the chipset.
•
DRAM Timing By SPD
This controls the SDRAM performance: default is “Enabled”. BIOS will auto detect the
SPD information of the Memory Module and choose the proper setting. “Disabled”
allows the timing to be set manually.
•
DRAM Clock
Set the clock frequency of the DRAMs. The default value is “Host CLK”. You can select
“HCLK+33M” if your DRAM modules are faster than the CPU (a 66MHz FSB CPU with
a PC100 SDRAM, or a 100MHz FSB CPU with PC133 SDRAM); or select “HCLK-33M”
for a faster CPU with slower SDRAMs.
•
SDRAM CAS Latency
This controls the SDRAM performance, default is “3” clocks. If your SDRAM DIMM
specification is 2 CAS latency, change “3” to “2” for better performance.
