BIOS SETUP
34
•
AGP Master 1 WS Read
This implements a single delay when reading to the AGP Bus. By default, two-wait states
are used by the system, allowing for greater stability.
•
AGP Fast Write
This field allows you to enable AGP Fast Write.
•
CPU & PCI Bus Control
This submenu controls the CPU and PCI Bus controller register.
•••••
CPU to PCI Write Buffer
If “Enabled” is selected, writes from the CPU to the PCI bus are buffered to compensate
for the speed differences between the CPU and the PCI bus. If “Disabled”, the writes are
not buffered and the CPU must wait until the write is complete before starting another
write cycle.
•
PCI Master 0 WS Write
When “Enabled”, writes to the PCI bus are executed with zero wait states.
•
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transaction
cycles. Selecting “Enabled” supports compliance with PCI specification version 2.1.
