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User's Manual l MBLS1028A UM 0100 l © 2020, TQ-Systems GmbH
Page 13
4.3.1.3
QSGMII
In addition to the Ethernet Controller (ENETC), the LS1028A CPU provides a TSN switch (Time-Sensitive Networking Switch)
that operates four external ports via SerDes.
The TSN switch is not routed via the Ethernet controller but via SerDes and is implemented as QSGMII.
The QSGMII interface includes PHY reset and interrupt signals.
When looking at the MBLS1028A from outside, X8 is on the left, X9 is on the right.
Figure 11: Block diagram Ethernet QSGMII
The following table shows the pinout of the Ethernet connectors X8, and X9.
Table 6:
Pinout Ethernet QSGMII, RJ-45 connectors X8, X9
RJ-45
X8
X9
Left
Right
Left
Right
Interface
P0_MDI
P1_MDI
P2_MDI
P3_MDI
Figure 12: Gbit ETH connectors X8, X9