User's Manual l MBLS1028A UM 0100 l © 2020, TQ-Systems GmbH
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4.3
Communication interfaces
4.3.1
Ethernet
4.3.1.1
RGMII
The LS1028A provides an RGMII Ethernet controller (EC1 – port 1). On the MBLS1028A the interface provides a Gigabit Ethernet
port. The PHY supports IEEE
®
802.3 10BASE-T, 100BASE-T, and 1000BASE-T.
The 125 MHz reference clock for the MAC of the CPU is generated by a quartz oscillator.
The RGMII interface contains PHY reset and interrupt signals. The PHY signals are routed to RJ-45 connector X6.
Figure 8:
Block diagram Ethernet RGMII
4.3.1.2
SGMII
The LS1028A provides an Ethernet controller (SGMII – port 0), which is used as SGMII interface via SerDes Lane 0.
On the MBLS1028A the interface provides a Gigabit Ethernet port.
The SGMII interface contains PHY reset and interrupt signals. The PHY signals are routed to RJ-45 connector X7.
Figure 9:
Block diagram Ethernet SGMII
Figure 10: Gbit ETH connectors X6, X7
