Preliminary User's Manual l MBLS1012AL UM 0001 l © 2019, TQ-Systems GmbH
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The RESET_REQ# signal enables the CPU to trigger a reset itself via software or in the event of an error (watchdog, security
violation, etc.).
The signals RESET_REQ# and RESET_1V8# are connected via DIP switch S1, slot 2. This enables to separate the connection
between the two signals. Thus an endless boot loop can be prevented in case of a missing RCW. This is necessary to install a new
RCW. See also section 4.4.
A diode is connected between RESET_REQ# and DIP switch. This prevents RCW_SRC from being pulled low during the reset
phase, thus loading the hard-coded RCW (see section 4.4).
Illustration 23:
Position of Reset LED
4.4
Boot-Mode configuration
The boot behaviour of the LS1012A is determined by a 512-bit Reset Configuration Word (RCW). This is loaded during normal
operation from the connected QSPI flash memory on the TQMLS1012AL. The processor only supports this one boot source.
In case the RCW on the QSPI flash is missing or damaged, a fallback mode exists to store a suitable boot configuration in the
memory. For this purpose a fixed standard configuration of the RCW (Hard-Coded RCW) is loaded, which provides the minimum
necessary values for the CPU to operate. This is activated via a boot strap resistor at RESET_REQ#.
By connecting the RESET_REQ# / RCW_SRC signal to DIP switch (S1) (see also section 4.5.1), the value assigned to cfg_rcw_src
determines one of the two possible RCW sources. The value is read in during Power-On-Reset and can be read out in CPU register
PORSR1[RCW_SRC]. For this purpose there is a pull-down resistor at the RESET_REQ# signal to select the Hard-Coded RCW during
the boot process (see following table).
Table 27:
Boot-Mode-Select values for cfg_rcw_src
cfg_rcw_src value
Selection on MBLS1012AL
RCW source
0
Slot 1 at DIP switch (S1) to ON
Hard-coded in CPU
1 (Default)
Slot 1 at DIP switch (S1) to OFF
QuadSPI (QSPI)
Attention: Missing RCW in QSPI flash
If no RCW is detected in the QSPI flash, the CPU automatically triggers a reset. See section 4.3.
