Preliminary User's Manual l MBLS1012AL UM 0001 l © 2019, TQ-Systems GmbH
Page 14
The JTAG test reset pin (TP18, JTAG_TRST#) must be grounded simultaneously with PORESET# during normal operation. This is
achieved by using a 0 Ω bridge on the MBLS1012AL. If a boundary-scan is to be performed, this bridge must be removed and
both signals must be controlled accordingly. The JTAG interface is not ESD protected.
The following table shows the pin assignment of the JTAG connector.
Table 15:
Pinout JTAG header X18
Pin
Pin name
Target pin / Net
1
VTref / (VCC
V_1V8
2
JTAG_CPU_TMS
JTAG_TMS (TP17)
3
GND
GND
4
JTAG_CPU_TCK
JTAG_TCK (TP16)
5
GND
GND
6
JTAG_CPU_TDO
JTAG_TDO (TP15)
7
KEY
NC
8
JTAG_CPU_TDI
JTAG_TDI (TP14)
9
GND_DETECT_1V8
GND_DETECT_3V3
10
JTAG_CPU_RESET#
RESET_IN#
Illustration 12:
Position of JTAG header X18