DTH7500 / DTH8000
First issue 12 / 03
SPDIF_ACLK
SPDIF_ACLK
VID_CLK
+12VS
VID_ACTIVE
27CK_ACLK_SYS
DGND
LOGGER_IRQ
LOGGER_CS
ADLRCLK
DAC_RST
ADSCLK
ADSCLK
DGND
ADLRCLK
ADSCLK
ADSDAT2
+5VS3D
PWR_OK
TO
AGND
SLIDE_OC
SLIDE_IN
SLIDE_OUT
+1V8SD
+3V3SD
+5VS5A
+3VS2A
+2V5SD
+5VS3D
3.3ISORT
3.3ISO
PWR_OK
ADMCLK
27CK_DXX
CLA_STCLK
168CK_ELM
CLA_SCLK
27CK_GS
48CK_USB
DGND
FROM
CE1
BBI2C_CLK1
BBI2C_DATA1
FROM
DVA_RST
USB+FRONT
USB-FRONT
3.3ISORT
3.3ISO
USB-FRONT
USB+FRONT
I2C_DATA
I2C_CLK
ODD_IRQ
ODD_RST
+8VS
+2V5SD
I2C_DATA
I2C_CLK
+5VS3D
AGND
VEISSYNC
VEI_SSTB
VEISRDY
VEISREQ
OSREQ
OSVLD
OSSYNC
VEISSYNC
OSREQ
OSSYNC
FROM
WE0
WE1
OE
I2C_CLK
TO
DASCLK
DAMCLK
WE0
EMI_AD[1:21]
EMI_D[0:15]
FROM
+1V8SD
B_OUT
G_OUT
+5VS5A
AGND
SLIDE_IN
DX_656D[0:7]
AV_MD[0:15]
AV_MA[0:13]
AV_QDMU
AV_QDML
AV_WE
AV_CAS
AV_CS0
RAS0
CAS0
FLASH_WR
CE3
MEMWAIT
+5VS3D
+3V3SD
+2V5SD
DGND
+5VS3D
+3V3SD
DGND
DGND
+3V3SD
AV_SDCLK
Y_OUT
C_OUT
PPC_CLK
48CK_USB
SLIDE_OUT
R_OUT
168CK_ELM
OS[0:7]
GS_IRQ1
DXXHSYNC
DXX_FLD
GS_IRQ0
FROM
DGND
+5VS3D
+3V3SD
+2V5SD
VDEC_RTS1
VDEC_RTS0
VDEC_HS
AGND_IN
+3V3SD
CIRCUIT DIAGRAM
BLOCK DIAGRAMS
+3V3SD
VDEC_VID[0:7]
FROM
CLA_STCLK
B_SYNC
B_DATA
B_FLAG
WE0
WE1
RNOTW
SLIDE_OC
GS_IRQ2
CE1
OE
RESET
SYS_RST
DALRCLK
27CK_GS
ACLK_27M
FROM
PPC_CLK
VDEC_VCLK
VDEC_RST_N
PSTOP
CLA_VIN[0:7]
CLA_HSYNC
CLA_VSYNC
CLA_FLDI
CLA_VCLKI
CLA_LRCK
CLA_BCK
CLA_ADATA
CLAHI_CWE
CLAHI_CRE
CLAHI_CCS
CLAHI_INT
CLA_ACLK
RESET
I2C_DATA
EMI_AD[1:21]
EMI_AD[1:21]
EMI_D[0:15]
TO
OSCLK/OSSTB
VEI_SSTB
VEISRDY
VEISREQ
ELMR_RST
ELMR_RST
ELMR_IRQ
ELMR_IRQ
FROM
TO
AV_RAS
DASDAT3
SYS_CS
E2PROM_EN
MEMWAIT
CLA_SCLK
EMI_D[0:15]
MODEM_RST
ODD_IRQ
ODD_RST
I2S_SEL
OSCLK/OSSTB
TO
FROM
FROM
RNOTW
CE2
ACLK_27M
FROM
TO
+8VS
MODEM_RST
FROM
ADLRCLK
I2S_SEL
CV_OUT
SPDIF_DXX
TO SHT
LOGGER_CS
27CK_DXX
LOGGER_IRQ
TO SHT
ADSDAT2
OS[0:7]
ADSCLK
ADLRCLK
ADSDAT2
FROM
DAC_RST
B_BCLK
CE2
AGND
DGND
IR_ELMER
IR_ELMER
BBI2C_DATA1
BBI2C_CLK1
BBI2C_CLK1
BBI2C_DATA1
PS_RST
27CK_ACLK_SYS
DVA_VPLL
MODEM_IRQ
ADMCLK
DVA_VPLL
MEMWAIT
+12VS
PS_V
OSVLD
DXX_VCLKO
21285810-00-3
+3V3SD
AGND
AGND_IN
BBI2C_CLK1
BBI2C_DATA1
DGND
VDEC_HS
VDEC_RST_N
VDEC_RTS0
VDEC_RTS1
VDEC_VCLK
VDEC_VID[0:7]
ENG:LICF
VIDEO_DECODER
SHEET 2 OF
9
+3V3SD
+5VS3D
+8VS
168CK_ELM
48CK_USB
B_BCLK
B_DATA
B_FLAG
B_SYNC
DGND
ELMR_IRQ
EMI_AD[1:21]
EMI_D[0:15]
I2C_CLK
I2C_DATA
I2S_SEL
IR_ELMER
MEMWAIT
ODD_IRQ
OS[0:7]
PPC_CLK
USB+FRONT
USB-FRONT
VEISRDY
VEISSYNC
VEI_SSTB
CE2
ELMR_RST
ODD_RST
RNOTW
VEISREQ
WE0
WE1
ENG:JACK
28300
ELMER
SHT 5
OF 9
+5VS3D
+5VS5A
ADLRCLK
ADSCLK
ADSDAT2
AGND
BBI2C_CLK1
BBI2C_DATA1
B_OUT
CV_OUT
C_OUT
DGND
G_OUT
R_OUT
SPDIF_ACLK
SPDIF_DXX
Y_OUT
DAC_RST
MPEG
DECODER
VOUT
ENG:CHEN
SHT 7
OF 9
FROM SHT
4
FROM SHT
4
TO SHT
7
SHT 6
TO SHT
6
FROM SHT
5
FROM SHT
3
SHT 4
SHT 5
SHT 9
TO SHT
7
SHT 3
SHT 5
SHT 9
TO SHT
2
FROM SHT
3
TO SHT
5
FROM SHT
4
FROM SHT
3
5 &
8
SHT 9
SHT 9
SHT 8
3 &
7
SHT 3
SHT 6
SHT 6
SHT 3
SHT 6
SHT 3
SHT 9
TO SHT
3
FROM SHT
4
FROM SHT
3
FROM SHT
3
SHT 6
SHT 3
TO SHT
6
TO SHT
3
TO SHT
4
TO SHT
5
FROM SHT
3
TO SHT
6
TO SHT
3
+2V5SD
+3V3SD
+5VS3D
27CK_ACLK_SYS
27CK_GS
3.3ISO
3.3ISORT
ACLK_27M
ADLRCLK
ADMCLK
ADSCLK
ADSDAT2
CLAHI_CCS
CLAHI_CRE
CLAHI_CWE
CLAHI_INT
CLA_ACLK
CLA_ADATA
CLA_BCK
CLA_FLDI
CLA_HSYNC
CLA_LRCK
CLA_VCLKI
CLA_VIN[0:7]
CLA_VSYNC
DALRCLK
DAMCLK
DASCLK
DASDAT3
DGND
DVA_VPLL
DXXHSYNC
DXX_FLD
DXX_VCLKO
DX_656D[0:7]
ELMR_IRQ
EMI_AD[1:21]
EMI_D[0:15]
GS_IRQ0
GS_IRQ1
GS_IRQ2
IR_ELMER
LOGGER_CS
LOGGER_IRQ
MEMWAIT
MODEM_IRQ
ODD_IRQ
OSCLK/OSSTB
OSREQ
OSSYNC
OSVLD
OS[0:7]
PSTOP
PS_V
PWR_OK
USB+FRONT
USB-FRONT
VDEC_HS
VDEC_RST_N
VDEC_RTS0
VDEC_RTS1
VDEC_VCLK
VDEC_VID[0:7]
VEISRDY
VEISSYNC
VEI_SSTB
VID_ACTIVE
VID_CLK
CE1
DAC_RST
DVA_RST
ELMR_RST
MODEM_RST
ODD_RST
OE
PS_RST
RESET
SYS_RST
VEISREQ
WE0
ENG:CAILB
(GOBSTOPPER)
BUFF_CF
SHEET 3 OF
9
+2V5SD
+3V3SD
ADLRCLK
ADSCLK
CLAHI_CCS
CLAHI_CRE
CLAHI_CWE
CLAHI_INT
CLA_ACLK
CLA_ADATA
CLA_BCK
CLA_FLDI
CLA_HSYNC
CLA_LRCK
CLA_SCLK
CLA_STCLK
CLA_VCLKI
CLA_VIN[0:7]
CLA_VSYNC
DGND
EMI_AD[1:21]
EMI_D[0:15]
OSCLK/OSSTB
OSREQ
OSSYNC
OSVLD
OS[0:7]
PSTOP
SPDIF_ACLK
DVA_RST
ENCODER
MPEG
ENG:JACK
SHEET 4 OF
9
+1V8SD
+2V5SD
+3V3SD
+5VS3D
27CK_DXX
ADLRCLK
ADSCLK
ADSDAT2
AGND
AV_MA[0:13]
AV_MD[0:15]
AV_QDML
AV_QDMU
AV_SDCLK
BBI2C_CLK1
BBI2C_DATA1
B_BCLK
B_DATA
B_FLAG
B_OUT
B_SYNC
CV_OUT
C_OUT
DALRCLK
DAMCLK
DASCLK
DASDAT3
DGND
DXXHSYNC
DXX_FLD
DXX_VCLKO
DX_656D[0:7]
EMI_AD[1:21]
EMI_D[0:15]
FLASH_WR
GS_IRQ0
GS_IRQ1
GS_IRQ2
G_OUT
I2C_CLK
I2C_DATA
I2S_SEL
MEMWAIT
MODEM_IRQ
PPC_CLK
PS_V
R_OUT
SLIDE_IN
SLIDE_OC
SLIDE_OUT
SPDIF_DXX
VID_ACTIVE
VID_CLK
Y_OUT
AV_CAS
AV_CS0
AV_RAS
AV_WE
CAS0
CE1
CE2
CE3
E2PROM_EN
MODEM_RST
OE
PS_RST
RAS0
RESET
RNOTW
SYS_CS
SYS_RST
WE0
WE1
BBI2C_CLK1
BBI2C_DATA1
WE0
MEMWAIT
ENG:CHEN
DECODER
MPEG
SHEET 6 OF
9
+12VS
+3V3SD
+5VS3D
AV_MA[0:13]
AV_MD[0:15]
AV_QDML
AV_QDMU
AV_SDCLK
DGND
EMI_AD[1:21]
EMI_D[0:15]
FLASH_WR
I2C_CLK
I2C_DATA
LOGGER_CS
LOGGER_IRQ
MEMWAIT
PPC_CLK
AV_CAS
AV_CS0
AV_RAS
AV_WE
CAS0
CE1
CE2
CE3
E2PROM_EN
OE
RAS0
RESET
RNOTW
SYS_CS
WE0
WE1
MEMORY
ENG:CHEN
SHT 8
OF 9
+12VS
+1V8SD
+2V5SD
+3V3SD
+3VS2A
+5VS3D
+5VS5A
+8VS
168CK_ELM
27CK_ACLK_SYS
27CK_DXX
27CK_GS
3.3ISO
3.3ISORT
48CK_USB
ACLK_27M
ADMCLK
AGND
CLA_SCLK
CLA_STCLK
DGND
DVA_VPLL
PWR_OK
SLIDE_IN
SLIDE_OC
SLIDE_OUT
ENG:JACK & CHANG
POWER CIRCUIT
CLOCK AND
SHT 9
OF 9
140103
(DIGITAL BOARD 1/9)
MAIN SCHEMATIC DIAGRAM - SCHEMA DE LA PLATINE PRINCIPALE - SCHALTBILD HAUPTPLATINE - SCHEMA DELLA PIASTRA PRINCIPALE- ESQUEMA DE LA PLATINA PRINCIPAL
