Preliminary
THCV245A_Rev.0.90_E
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6.34 Power On Sequence
Power On Sequence must be controlled appropriate.
MIPI, PLL and V-by-One® HS block are reset state at power on default and require Reset Release.
. MIPI Soft Reset / PLL Soft Reset => V-by-One® HS Soft Reset is proper. See below detail.
Figure 21.
Power On Sequence procedure
Table 53.
Power On Sequence specification
VDDIO/VDDB
(3.3V-1.8V)
VDDL/VDDM/VDDA
/VDDOP(1.2V)
Register Access
CKI(Ref Clock)
Initial Register setting is needed
REG(R_RX_CKOSTOP)
REG(R_PLL_SNRST)
REG(R_VX1_SNRST)
REG(R_PLL_SNRST) Soft Reset must be released
after all PLL setting parameters are completely written.
t1
t5
t6
tLT
TX0P/TX0N (,TX1P/TX1N)
tTPLL0
REG(R_TX_SNRST) Soft Reset must be released
after all Vx1HS TX setting paremeters written and PLL locked.
To force REG(R_CKOSTOP) Low makes CKO pin start output
REG(R_RX_DATALANE_EN)
REG(R_RX_CLKLANE_EN)
RCKP/RCKN
MIPI Lane Enable are supposed to be activated at mipi LP mode timing.
Sequence should be from Data Lane (0x102D) to Clock Lane (0x102C).
CKO
Register Access Time
t3
PDN0
Wait time before Register access is required after PDN=L => H
LP mode
HS mode
Symbol
Parameter
Min
Typ
Max
Unit
t1
3.3V to 1.2V
0
-
-
us
t3
PDN0 Reset Rerease Time
0
-
-
us
t5
Required w ait from PDN0=H to Register Access
300
-
-
us
t6
Required w ait from CKI input to PLL Enable
200
-
-
us
tLT
Required w ait from PLL Lock Time to CML output
-
-
us
tTPLL0
V-by-One® HS Reset Release to CML Out Delay
-
-
250
us
1000
F(CKI)
