Preliminary
THCV245A_Rev.0.90_E
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In principle, when Sub-Link bridges 2-wire serial interface communication from Sub-Link Master to Sub-Link
Slave or remote side 2-wire serial slave devices, time lag occurs between HOST MPU side 2-wire serial access
and Sub-Link Slave internal bus access or remote side 2-wire serial access.
R_2WIRE_CLKSEN (Sub-Link Master side register, 0x0042 bit0) selects whether 2-wire serial slave of Sub-
Link Master perform clock stretching.
When R_2WIRE_CLKSEN = 1, Sub-Link Master device waits HOST MPU until Sub-Link Slave register access
or remote side 2-wire serial slave register access complete by clock stretching.
When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register
access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without
clock stretching.
Figure 18.
Sub-Link Master 2-wire slave clock stretching operation
