SLOS787H – MAY 2012 – REVISED APRIL 2014
5.3
Electrical Characteristics
TYP operating conditions are T
A
= 25°C, VIN = 5 V, full-power mode (unless otherwise noted)
MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
All building blocks disabled, including supply-
I
PD1
Supply current in Power Down Mode 1
voltage regulators; measured after 500-ms
0.5
5
µA
settling time (EN = 0, EN2 = 0)
The SYS_CLK generator and V
DD_X
remain
Supply current in Power Down Mode 2
I
PD2
active to support external circuitry; measured
120
200
µA
(Sleep Mode)
after 100-ms settling time (EN = 0, EN2 = 1)
Oscillator running, supply-voltage regulators in
I
STBY
Supply current in stand-by mode
1.9
3.5
mA
low-consumption mode (EN = 1, EN2 = x)
Supply current without antenna driver
Oscillator, regulators, RX and AGC active, TX
I
ON1
10.5
14
mA
current
is off
Oscillator, regulators, RX and AGC and TX
I
ON2
Supply current – TX (half power)
70
78
mA
active, P
OUT
= 100 mW
Oscillator, regulators, RX and AGC and TX
I
ON3
Supply current – TX (full power)
130
150
mA
active, P
OUT
= 200 mW
V
POR
Power-on reset voltage
Input voltage at V
IN
1.4
2
2.6
V
V
BG
Bandgap voltage (pin 11)
Internal analog reference voltage
1.5
1.6
1.7
V
Regulated output voltage for analog
V
DD_A
V
IN
= 5 V
3.1
3.4
3.8
V
circuitry (pin 1)
V
DD_X
Regulated supply for external circuitry
Output voltage pin 32, V
IN
= 5 V
3.1
3.4
3.8
V
I
VDD_Xmax
Maximum output current of V
DD_X
Output current pin 32, V
IN
= 5 V
20
mA
Half-power mode, V
IN
= 2.7 V to 5.5 V
8
12
R
RFOUT
Antenna driver output resistance
(1)
Ω
Full-power mode, V
IN
= 2.7 V to 5.5 V
4
6
R
RFIN
RX_IN1 and RX_IN2 input resistance
4
10
20
k
Ω
Maximum RF input voltage at RX_IN1 and
V
RF_INmax
V
RF_INmax
should not exceed V
IN
3.5
V
pp
RX_IN2
f
SUBCARRIER
= 424 kHz
1.4
2.5
Minimum RF input voltage at RX_IN1 and
V
RF_INmin
mV
pp
RX_IN2 (input sensitivity)
(2)
f
SUBCARRIER
= 848 kHz
2.1
3
f
SYS_CLK
SYS_CLK frequency
In power mode 2, EN = 0, EN2 = 1
25
60
120
kHz
f
C
Carrier frequency
Defined by external crystal
13.56
MHz
Time until oscillator stable bit is set (register
t
CRYSTAL
Crystal run-in time
3
ms
0x0F)
(3)
Depends on capacitive load on the I/O lines,
f
D_CLKmax
Maximum DATA_CLK frequency
(4)
2
8
10
MHz
recommendation is 2 MHz
(4)
R
OUT
Output resistance I/O_0 to I/O_7
500
800
Ω
R
SYS_CLK
Output resistance R
SYS_CLK
200
400
Ω
(1)
Antenna driver output resistance
(2)
Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1.
(3)
Depends on the crystal parameters and components
(4)
Recommended DATA_CLK speed is 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not
exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output
resistance of 400
Ω
(12-ns time constant when 30-pF load used).
10
Specifications
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