Low Dropout Voltage Linear Regulator Circuit Operation
1-2
Introduction
1.1
Low Dropout Voltage Linear Regulator Circuit Operation
In TI’s low dropout voltage linear regulator topology, a PMOS transistor acts
as the pass element. Because the PMOS device behaves as a low-value
resistor, the dropout voltage is very low and is directly proportional to the output
current. Additionally, since the PMOS pass element is a voltage-driven device,
the quiescent current is very low and independent of output loading.
The basic LDO regulator circuit includes the LDO and an output capacitor for
stabilization. Figure 1–1 shows the circuit of a typical LDO application.
Figure 1–1. Typical LDO Application
_
+
Control
_
+
R1
R2
Q1
V
ref
LDO
C
O
V
O
Load
_
+
V
CC
In the LDO application shown in Figure 1–1, the LDO regulates the output
voltage V
O
.
If V
O
falls below the regulation level, the controller increases the V
SG
differential and the PMOS transistor conducts more current, resulting in an
increase in V
O
. If V
O
exceeds the regulation level, the controller decreases the
V
SG
differential and the PMOS transistor conducts less current, resulting in a
decrease in V
O
. The PMOS pass element acts like an adjustable resistor. The
more negative the gate becomes versus the source, the less the source-drain
resistance becomes, resulting in higher current flow through the PMOS.