ESR and Transient Response
3-3
Circuit Design
Figure 3–2 shows the output capacitor and its parasitic impedances in a typical
LDO output stage.
Figure 3–2. LDO Output Stage With Parasitic Resistances ESR
–
LDO
V
I
V
ESR
I
O
R
ESR
C
O
R
LOAD
V
O
+
+
–
In steady state (dc state condition), the load current is supplied by the LDO
(solid arrow) and the voltage across the capacitor is the same as the output
voltage (V(C
O
) = V
O
). This means no current is flowing into or out of the C
O
branch.
If I
O
suddenly increases (transient condition), the LDO is not able to supply the
sudden current need due to its response time (t
1
in Figure 3–3). Therefore, ca-
pacitor C
O
provides the current for the new load condition (dashed arrow). C
O
now acts like a battery with an internal resistance, R
ESR
. Depending on the
current demand at the output, a voltage drop will occur at R
ESR
. This voltage
is shown as V
ESR
in Figure 3–2.
When C
O
is conducting current to the load, initial voltage at the load will be
V
O
= V(C
O
) – V
ESR
. Due to the discharge of C
O
, the output voltage V
O
will drop
continuously until the response time t
1
of the LDO is reached and the LDO will
resume supplying the load. From this point, the output voltage starts rising
again until it reaches the regulated voltage. This period is shown as t
2
in
Figure 3–3.
The figure also shows the impact of different ESRs on the output voltage. The
left brackets show different levels of ESRs where number 1 displays the lowest
and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
-
The higher the ESR, the larger the droop at the beginning of load transient.
-
The smaller the output capacitor, the faster the discharge time and the big-
ger the voltage droop during the LDO response period.
3.2.1
Conclusion
To minimize the transient output droop, capacitors must have a low ESR and
be large enough to support the minimum output voltage requirement for a
given LDO response time.