Test Results
4-4
Test Results
Figure 4–5. Timing When SEQUENCE = Low, Including RESET
V
IN1 =
V
IN2
at 5V and both V
OUT1
(CH1) and V
OUT2
(CH2) have no load. EN
is pulsed with a fast pulse. V
OUT1
powers up before V
OUT2
when SEQUENCE
= low. PG_1 (CH3), tied to MR1, goes high when V
OUT1
reaches 95% of
regulated voltage. After a 120 ms delay, RESET (CH4) is being driven by both
V
OUT1
and V
OUT2
power good.
Figure 4–6. Timing When SEQUENCE = High
V
IN1 =
V
IN2
at 5V and both V
OUT1
(CH1) and V
OUT2
(CH2) have no load. EN
is pulsed with a fast pulse. V
OUT2
powers up before V
OUT1
when SEQUENCE
= high. PG_1 (CH3), tied to MR1, goes high when V
OUT1
reaches 95% of
regulated voltage.