Test Results
4-5
Test Results
Figure 4–7. Timing When SEQUENCE = High and V
OUT1
Faults Out
When SEQUENCE = high, V
OUT2
(CH2) remains on even after V
OUT1
(CH1)
faults out due to current limit. The V
OUT1
fault causes PG_1 (CH3), tied to
MR1, to go low. MR1 causes RESET (CH4) to go low.
Figure 4–8. Timing When SEQUENCE = High and V
OUT2
Faults Out
When SEQUENCE = high and V
OUT2
(CH2) faults out due to current limit,
V
OUT1
(CH1) is disabled and PG_1 (CH3), tied to MR1, goes low. The V
OUT2
fault causes RESET (CH4) to go low.