Texas Instruments TPS6593EVM, Руководство пользователя

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The J29 signal, nPWRON_S, and the nPWRON/ENABLE or VOUT_LDOVINT signals of the PMIC are
connected through J37. When multiple PMICs are stacked, as shown in
Figure 3-6 , the expectation is that the
master is placed in master mode, connecting the stackable signal nPWRON_S, and the VOUT_LDOVINT. By
using this stackup configuration, one or more of the slaves power up sequence will always follow the master.
When in master mode or when the header J37 is left open the nPWRON/ENABLE pin can be controlled with the
EVM push button, S1, or the jumper J45.
2
Master
VOUT_LDOVINT
nPWRON_S
nPWRON/ENABLE
J37
J29
Slave
VOUT_LDOVINT
nPWRON/ENABLE
J37
J29
Slave
nPWRON_S
VOUT_LDOVINT
nPWRON_S
nPWRON/ENABLE
J37
J29
Figure 3-6. Header J37 Master and Slave Select Table Description for 'OPEN' configuration
Table 3-9. Header J37 Master and Slave Select
Configuration Description
Open When used as a single PMIC (no stacking). ENABLE is connected to
a pullup and therefore automatically enabled. S1 can be used to
generate edges or J45 at any level.
3
Slave, M/S Select: Closed Slave Mode. The PMIC signal ENABLE is connected to the
nPWRON_S signal which is from the master's VOUT_LDOVINT.
M/S Select, Master: Closed Master Mode. The PMIC signal, VOUT_LDOVINT, is connected to
the nPWRON_S which will be the ENABLE signal on the PMICs
connected as slaves.
2
The default position for J45 is with pins 1-2 closed so that the pullup is applied to nPWRON/ENABLE.
3
The default position for J45 is with pins 1-2 closed so that the pullup is applied to nPWRON/ENABLE. J45
is provided so that the signal nPWRON/ENABLE can be pulled low or sourced from an off board signal.
EVM Details www.ti.com
12 TPS6594x-Q1 Evaluation Module SLVUBT0A – JUNE 2020 – REVISED JANUARY 2021
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