Texas Instruments TPS6593EVM, Руководство пользователя

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Figure 3-3. LDO_Headers_v2
Note
J13 and J14 provide the same LDO outputs; however, J13 should only be used for probing. J14
provides a shorter and wider trace, lowering the impedance and supporting maximum loads of 500
mA. Also, pin 7 is a different signal for J13 and J14; GND_S and AMUXOUT, respectively.
Signal Header J12 provides access to all of the buck regulator outputs, GND_S and VCCA_S.
Note
Header J12 should only be used for voltage probing and not for power delivery.
GPIO signals are provided on both J9 and J11. J8 (PU) is located directly above J9 enabling each GPIO to be
pulled to the voltage defined in table
Table 3-8 through a 10 kΩ resistor pullup. J10 (PD) is located directly below
J9 to enable shorting each GPIO directly to GND.
Table 3-8. Header J8 Pullup Voltages
J8, Pin(s) Pullup Voltage Description
1,2,7-11 VIO_IN GPIO1, GPIO2, GPIO7-11: Output Type Selection; Power Domain is VIO
3,4 VOUT_LDOVRTC GPIO3 and GPIO4: Input Type Selection; Power Domain is VRTC
5,6 VOUT_LDOVINT GPIO5 and GPIO6: Output Type Selection; Power Domain is VINT
3.6 Stack-Up Headers
As shown in Figure 3-4 , multiple boards can be configured into a master-slave relationship (1 master and up to 5
slaves) and physically stacked upon each other. VCCA and GND are shared between boards on headers J27
and J28. Communication between the boards is shared on header J29. This header, J29, is marked on the
bottom silkscreen, as shown in
Figure 3-5 .
EVM Details www.ti.com
10 TPS6594x-Q1 Evaluation Module SLVUBT0A – JUNE 2020 – REVISED JANUARY 2021
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