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VCCA

SW_B1

OSC32KOUT

OVPGDRV

FB_B1

VCCA

DNP

47µF

C24

L1 470nH

10V

DNP

47mF

DNP

VOUT_B1

L2 470nH

L3 470nH

L4 470nH

L5 470nH

VOUT_LDOVRTC

VOUT_LDO1

VSYS

680 µF

C79

DNP

AMUXOUT

C55

10uF

TP1

TP2

10k

R27

2.2uF

C10

2.2uF

C11

2.2uF

C12

2.2uF

C13

2.2uF

C15

VIO_IN

SW_B2

SW_B3

SW_B4

SW_B5

FB_B2

FB_B3

FB_B4

FB_B5

FB_B1

FB_B3

FB_B4

FB_B5

FB_B2

Phase Config

R2/R3

R4/R5

R6/R7

J23 J24

J25

1 (4)

2 (3+1)

3 (2+1+1)

4 (1+1+1+1)

5 (2+2)

J16

DNP

J17

DNP

VOUT_B1

VOUT_B2

VOUT_B3

VOUT_B1

VOUT_B3

VOUT_B4

240

R20

DNP

240

R21

DNP

10k

VIO_IN

PVIN_LDO4

VOUT_LDO4

DNP

150uF

0.002

R25

10k

R28

VOUT_LDO3

PVIN_LDO3

2.2uF

VCCA

SDA_I2C1/SDI_SPI

SCL_I2C1/SCK_SPI

0.47uF

C14

10uF

C36

0.1 µF

C35

0.1 µF

C39

47µF

C29

1µF

C68

22uF

C18

47µF

C25

VOUT_B2

47µF

C30

22uF

C19

47µF

C26

47µF

C31

22uF

C20

47µF

C27

47µF

C32

22uF

C21

47µF

C28

47µF

C33

22uF

C22

VOUT_B3

VOUT_B4

VOUT_B5

C63

10uF

1µF

C74

C60

10uF

0.1 µF

C40

0.1 µF

C43

1µF

C71

C65

10uF

1µF

C76

C61

10uF

0.1 µF

C41

0.1 µF

C44

1µF

C72

C66

10uF

1µF

C77

C59

10uF

0.1 µF

C37

0.1 µF

C42

1µF

C70

C64

10uF

1µF

C75

C54

10uF

0.1 µF

C34

0.1 µF

C38

1µF

C67

47µF

C45

47µF

C49

C62

10uF

1µF

C73

0.1 µF

C23

2.2uF

J32

DNP

J33

DNP

J35

DNP

J34

DNP

GPIO3

GPIO4

GPIO7

GPIO8
GPIO9

GPIO11

GPIO7

DNP

R67

nPWRON

J36

DNP

10uF

C47

R26

DNP

µF

C46

47µF

C50

47µF

C51

47µF

C56

47µF

C52

47µF

C57

47µF

C48

47µF

C53

For LDOs PSRR, line and load

regulation measurements

32.768kHz

2
3

J18

1
2
3

J19

J20

J21

1
2
3

J26

10uF

C58

10uF

C69

10uF

C78

J23

DNP

VOUT_B2

VOUT_B3

VOUT_B1

VOUT_B4

VOUT_LDOVINT

VOUT_LDOVRTC

VIO_IN

1.2k

R22

DNP

1.2k

R23

1.2k

R24

GPIO11

TP9

DNP

TP10

DNP

TP11

DNP

TP12

DNP

TP13

DNP

SCLK_SPMI

SDATA_SPMI

nERR_SoC

nERR_MCU

GPIO2

GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11

VOUT_LDOVINT

VOUT_LDOVRTC

VOUT_LDO1
VOUT_LDO2
VOUT_LDO3
VOUT_LDO4

VOUT_B1
VOUT_B2
VOUT_B3
VOUT_B4
VOUT_B5

TP6

TP7

R35

DNP

R36

22uF

DNP

22uF

C94

DNP

GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11

10k

R10

10k

R11

10k

R12

10k

R13

10k

R14

10k

R15

10k

R16

10k

R17

10k

R18

GPIO1

VCCA_S

GPIO3

TP8

GPIO1

GPIO10

0.1µF

C93

3300pF

C102

0.1µF

C99

3300pF

C104

0.1µF

C100

3300pF

C103

3300pF

C101

3300pF

C105

VSYS

VCCA

VIO_IN

VCCA_S

R40

40V

DNP

1
2
3

6
7

J13

1
2
3

6
7

J12

R58

R65

6pF

C16

DNP

6pF

C17

DNP

22uF

SCL_I2C2/CS_SPI

SDA_I2C2/SDO_SPI

2
3

6
7

J14

AMUXOUT

TRIG_WDG

SYNCCLKIN

1
2
3

6
7
8
9
10
11

1
2
3

6
7
8
9
10
11

1
2
3

6
7
8
9
10
11

1
2
3

6
7
8
9
10
11

J10

1
2
3

6
7
8
9
10
11

J11

GPIO1

100

R32

GPIO1

GPIO2

VIO_IN

nPWRON

VSYS

SPI_EN

OVPGDRV

VSYS_SENSE

R19

100

R51

100

R54

R39

DNP

R83

1
2
3

6
7
8
9
10
11

J15

U2A

V+

V-

U2E

U2B

10k

R37

10k

R38

GNDS

NT1

Force

Sense

MCUVCC

NT2

NT3

TP3

-4

TP4

-4

TP5

-4

TP14

-4

J24

DNP

J25

DNP

MCUVCC

GND

PGND

GND

TPS60110PWPR

2.2uF

U14B

C115

V5V0

SYNC

ENABLE

OUT

C1+

C1-

C2-

C2+

OUT

SKIP

COM

CLK

TPS60110PWPR

U14A

2.2uF

C116

22uF

C113

22uF

C112

V5V0

R56

R57

R84

R85

R86

R87

R88

R89

R90

R91

R92

EN1

EN2

GND

OUT2

OUT1

TLV7103318QDSERQ1

U13

+VBUS

V3V3

2.2uF

C111

VOUT_LDOVINT

2
3

J39

DNP

J42

DNP

J43

DNP

J44

DNP

2
3

J40

DNP

2
3

J41

DNP

J47

DNP

10uF

C114

OSC32KCAP

VOUT_LDO2
VOUT_LDO3

VOUT_LDO4
VOUT_LDOVINT

OSC32KIN

PVIN_LDO4

PVIN_LDO12
PVIN_LDO3

2.2uF

nPWRON_S

VOUT_LDOVINT

10k

R33

1
2
3

J37

nPWRON

VCCA

0.1µF

C106

240

R30

1
2
3

J45

nRSTOUT
EN_DRV

nINT

VOUT_LDO2

OSC32KIN

GPIO2

SW_B2

SW_B5

REFGND2

PVIN_B2

GPIO4

VSYS_SENSE

VOUT_LDO3

INT

OVPGDRV

VOUT_LDOVRTC

PVIN_LDO12

REFGND1

FB_B3

VOUT_LDO4

RSTOUT

PVIN_B4

GND

EN_DRV

GPIO8

SDA_I2C1/SDI_SPI

FB_B1

VOUT_LDO1

OSC32KCAP

SCL_I2C1/SCK_SPI

PVIN_B1

GPIO5

GPIO6

GPIO7

GPIO9

SW_B3

VIO_IN

SW_B3

SW_B1

VOUT_LDOVINT

VCCA

PVIN_B3

PWRON/ENABLE

GPIO10

VBACKUP

SW_B4

PVIN_LDO3

SW_B2

PVIN_B5

FB_B5

SW_B4

FB_B2

AMUXOUT

OSC32KOUT

GPIO1

FB_B4

GPIO11

SW_B1

PVIN_LDO4

GPIO3

TPS65941-Q1

nINT

nINT
nRSTOUT

EN_DRV

nINT

Note:
Jumper on J37-2-3 for Master to provide
power on signal (LDOVINT) for slaves; all
slaves jumper on J37-1-2 to get power on
signal (ENABLE) from master. No jumper
on J37 when single PMIC is used.

Figure 5-3. TPS6593EVM 1+1+1+1+1 Configuration, Schematic Page 1

www.ti.com

Schematic, Layout, and Bill of Materials

SLVUBT0A – JUNE 2020 – REVISED JANUARY 2021

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TPS6594x-Q1 Evaluation Module

Содержание TPS6593EVM

Страница 1: ...eaders 9 3 6 Stack Up Headers 10 3 7 Connectors 13 3 8 EVM Control GPIO and Additional Regulators 13 4 Customization 13 4 1 Changing the Communication Interface 13 4 2 Changing the Phase Configuration 16 5 Schematic Layout and Bill of Materials 17 6 Additional Resources 37 7 Revision History 37 List of Figures Figure 2 1 TPS6594EVM Top View 4 Figure 2 2 TPS6593EVM Top View 4 Figure 3 1 TPS6594EVM ...

Страница 2: ...PS6594EVM Header J7 Description 8 Table 3 5 Header J26 VBACKUP 9 Table 3 6 Header J30 VIO_IN Voltage Select 9 Table 3 7 Header J15 V3V3 VSYS V5V0 GPIO1 I2C SPI 9 Table 3 8 Header J8 Pullup Voltages 10 Table 3 9 Header J37 Master and Slave Select 12 Table 3 10 EVM LED Indicators 13 Table 5 1 TPS6594EVM Bill of Materials of Balance of Components 27 Table 5 2 TPS6593EVM Bill of Materials of Balance o...

Страница 3: ...getting started and to accelerate development Table 1 1 EVM Descriptions PMIC Device Part Number Mode NVM Phase Configuration Components on the Back Side of the EVM EVM Part Number R1 R7 J23 J24 J25 PTPS65940400RWERQ1 Single PMIC 1 1 1 1 R1 R3 R5 R7 None TPS6594EVM PTPS65930400RWERQ1 Single PMIC 1 1 1 1 R1 R3 R5 R7 None TPS6593EVM 2 Getting Started The USB must be connected to a host PC in order t...

Страница 4: ...594EVM Top View Figure 2 2 TPS6593EVM Top View Getting Started www ti com 4 TPS6594x Q1 Evaluation Module SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Страница 5: ...ics of the slave EVM are the PMIC the backside components described in Figure 4 3 and the jumper position on J37 With the jumper on J37 placed in the slave position the ENABLE pin of the slave PMIC is connected to the VOUT_LDOINT output pin of the master PMIC through the J29 Stack up header Once the master and slave devices are stacked supplying power on J6 is the only requirement for getting star...

Страница 6: ...ess specifically described the features are the same between the TPS6594EVM and the TPS6593EVM 3 2 Terminal Blocks The terminal blocks are simple push and release terminals which can accommodate wire sizes up to 14 AWG Table 3 2 lists the terminal blocks found around the perimeter of the EVM J6 VSYS is the input voltage for all regulators BUCK and LDO 1 The remaining 5 terminal blocks are the BUCK...

Страница 7: ...14 GND NA 3 4 Configuration Headers There are six headers available to configure the EVM function Headers J26 and J37 configure the backup power supply and master and slave mode of operation respectively J45 is connected to J37 which can pull the nPWRON ENABLE pin of the PMIC to a logic high or low Header J7 as shown in the silk screen picture in Figure 3 1 and Figure 3 2 is used to configure the ...

Страница 8: ...ternative function to support SPI communication This setting is done in conjunction with J15 GPIO1 SCL2 CS Closed ERR_SoC GPIO3 Open Default GPIO mode GPIO3 of the PMIC is connected to PP5 of the through a level translator Closed SoC Error Count Down mode GPIO3 of the PMIC should be in the Alternative function to support the system error count down from the SoC GPIO is connected to alternative MCU...

Страница 9: ...e MCU SCL2 CS GPIO1 Closed Default I2C mode J7 SPI_EN Open Q A Watchdog mode GPIO1 of the PMIC should be in the Alternative function to support the Q A Watchdog and the I2C mode selected This setting is done in conjunction with J7 GPIO2 SDA2 SDO Closed SPI mode J7 SPI_EN Closed SPI mode Chip Select GPIO1 of the PMIC should be in the Alternative function to support SPI communication This setting is...

Страница 10: ... J9 to enable shorting each GPIO directly to GND Table 3 8 Header J8 Pullup Voltages J8 Pin s Pullup Voltage Description 1 2 7 11 VIO_IN GPIO1 GPIO2 GPIO7 11 Output Type Selection Power Domain is VIO 3 4 VOUT_LDOVRTC GPIO3 and GPIO4 Input Type Selection Power Domain is VRTC 5 6 VOUT_LDOVINT GPIO5 and GPIO6 Output Type Selection Power Domain is VINT 3 6 Stack Up Headers As shown in Figure 3 4 multi...

Страница 11: ... Slave Configuration Figure 3 5 EVM Bottom View Version 2 www ti com EVM Details SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback TPS6594x Q1 Evaluation Module 11 Copyright 2021 Texas Instruments Incorporated ...

Страница 12: ...der J37 Master and Slave Select Configuration Description Open When used as a single PMIC no stacking ENABLE is connected to a pullup and therefore automatically enabled S1 can be used to generate edges or J45 at any level 3 Slave M S Select Closed Slave Mode The PMIC signal ENABLE is connected to the nPWRON_S signal which is from the master s VOUT_LDOVINT M S Select Master Closed Master Mode The ...

Страница 13: ...f the pullup resistors is for I2C mode only and is only intended for one board in a stack up application Note in the stack up configuration only one board can have a valid VBUS voltage on the board This means that the master board can have a connected USB cable supplying VBUS or that VSYS can be connected to VBUS through J15 see Table 3 6 The EVM has 4 LEDs to indicate board power on or off and so...

Страница 14: ...S6594EVM Interface Settings for Communication Customization www ti com 14 TPS6594x Q1 Evaluation Module SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Страница 15: ...ice ID and therefore the chip select is used to determine which PMIC will receive and respond to commands on the SPI bus The signals SCL2 CS and GPIO1 on J15 should only be jumpered on the EVM which is intended to communicate with the GUI through the micro controller All other EVMs which are stacked should pull GPIO1 high so that the PMIC does not respond or interfere with the SPI communication No...

Страница 16: ... independent feedback circuits which can be configured to measure external supplies FB_B3 and FB_B4 are made available on test points TP6 and TP7 respectively If the voltage monitors associated with BUCK3 and BUCK4 are disabled then it is recommended to connect the FB_Bn pins to reference ground using R4 and R6 Figure 4 3 Phase Configuration Components Customization www ti com 16 TPS6594x Q1 Evalu...

Страница 17: ...µF C100 3300pF C103 3300pF C101 3300pF C105 VSYS VCCA VIO_IN VCCA_S 0 R40 40V D2 DNP 5 4 1 2 3 6 7 J13 5 4 1 2 3 6 7 J12 0 R58 0 R65 6pF C16 DNP 6pF C17 DNP 22uF C7 SCL_I2C2 CS_SPI SDA_I2C2 SDO_SPI 5 4 1 2 3 6 7 J14 AMUXOUT TRIG_WDG TRIG_WDG SYNCCLKIN 5 4 1 2 3 6 7 8 9 10 11 J7 5 4 1 2 3 6 7 8 9 10 11 J8 5 4 1 2 3 6 7 8 9 10 11 J9 5 4 1 2 3 6 7 8 9 10 11 J10 5 4 1 2 3 6 7 8 9 10 11 J11 GPIO1 100 R...

Страница 18: ...DA_I2C1 SDI_SPI nPWRON_S IO1 IO11 nINT3P3 100 R45 1 0M R68 1 0M R69 1 0M R60 2 2uF C85 2 2uF C86 2 2uF C88 1 0k R61 1 2k R50 SCL_I2C1 SCK_SPI 2 2uF C91 2 2uF C97 2 2uF C96 2 2uF C81 MCUVCC IO1 200k R53 1 0M R55 374k R66 0 1uF C98 GND 1 SREF 2 S1 3 S2 4 S3 5 S4 6 S5 7 S6 8 S7 9 S8 10 D8 11 D7 12 D6 13 D5 14 D4 15 D3 16 D2 17 D1 18 DREF 19 GREF 20 SN74GTL2003PWR U9 GND 1 SREF 2 S1 3 S2 4 S3 5 S4 6 S...

Страница 19: ... C100 3300pF C103 3300pF C101 3300pF C105 VSYS VCCA VIO_IN VCCA_S 0 R40 40V D2 DNP 5 4 1 2 3 6 7 J13 5 4 1 2 3 6 7 J12 0 R58 0 R65 6pF C16 DNP 6pF C17 DNP 22uF C7 SCL_I2C2 CS_SPI SDA_I2C2 SDO_SPI 5 4 1 2 3 6 7 J14 AMUXOUT TRIG_WDG TRIG_WDG SYNCCLKIN 5 4 1 2 3 6 7 8 9 10 11 J7 5 4 1 2 3 6 7 8 9 10 11 J8 5 4 1 2 3 6 7 8 9 10 11 J9 5 4 1 2 3 6 7 8 9 10 11 J10 5 4 1 2 3 6 7 8 9 10 11 J11 GPIO1 100 R32...

Страница 20: ...DA_I2C1 SDI_SPI nPWRON_S IO1 IO11 nINT3P3 100 R45 1 0M R68 1 0M R69 1 0M R60 2 2uF C85 2 2uF C86 2 2uF C88 1 0k R61 1 2k R50 SCL_I2C1 SCK_SPI 2 2uF C91 2 2uF C97 2 2uF C96 2 2uF C81 MCUVCC IO1 200k R53 1 0M R55 374k R66 0 1uF C98 GND 1 SREF 2 S1 3 S2 4 S3 5 S4 6 S5 7 S6 8 S7 9 S8 10 D8 11 D7 12 D6 13 D5 14 D4 15 D3 16 D2 17 D1 18 DREF 19 GREF 20 SN74GTL2003PWR U9 GND 1 SREF 2 S1 3 S2 4 S3 5 S4 6 S...

Страница 21: ...Layout Top Layer 1 www ti com Schematic Layout and Bill of Materials SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback TPS6594x Q1 Evaluation Module 21 Copyright 2021 Texas Instruments Incorporated ...

Страница 22: ...ayout Ground Layer 2 Schematic Layout and Bill of Materials www ti com 22 TPS6594x Q1 Evaluation Module SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Страница 23: ...ayout Signal Layer 3 www ti com Schematic Layout and Bill of Materials SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback TPS6594x Q1 Evaluation Module 23 Copyright 2021 Texas Instruments Incorporated ...

Страница 24: ...ayout Signal Layer 4 Schematic Layout and Bill of Materials www ti com 24 TPS6594x Q1 Evaluation Module SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Страница 25: ...ayout Ground Layer 5 www ti com Schematic Layout and Bill of Materials SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback TPS6594x Q1 Evaluation Module 25 Copyright 2021 Texas Instruments Incorporated ...

Страница 26: ...10 Layout Bottom Schematic Layout and Bill of Materials www ti com 26 TPS6594x Q1 Evaluation Module SLVUBT0A JUNE 2020 REVISED JANUARY 2021 Submit Document Feedback Copyright 2021 Texas Instruments Incorporated ...

Страница 27: ...45 C46 C48 C49 C50 C51 C52 C53 C56 C57 10 Chip Multilayer Ceramic Capacitors for Automotive 1206 3216 Metric GCM31CD70G476ME C54 C55 C59 C60 C61 C62 C63 C64 C65 C66 10 10 µF CAP CERM 10 µF 4 V 20 1 6x0 8mm 1 6x0 8mm NFM18HC106D0G3 C67 C68 C70 C71 C72 C73 C74 C75 C76 C77 C84 11 3 Terminals Chip Multilayer Ceramic Capacitor EMIFIL 0402 NFM15HC105D0G3 C80 C101 C102 C103 C104 C105 6 3300pF CAP CERM 33...

Страница 28: ...m 470 nH 5 3 A 0 021 Ω AEC Q200 Grade 0 SMD TDK Inductor TFM322512ALMAR47MTAA LBL1 1 PCB Label 0 650 x 0 200 inch THT 14 423 10 Q1 1 30V MOSFET N CH 30 V 27 2 A AEC Q101 SO 8FL SO 8FL NVMFS4C05NT1G R1 R3 R5 R7 R19 R26 R35 R36 R39 R40 R56 R57 R58 R65 R67 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 25 0 RES 0 5 0 063 W AEC Q200 Grade 0 0402 0402 RK73Z1ETTP R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R27 R...

Страница 29: ...plated Black Shunt 2 pos 100 mil 881545 2 TP1 TP2 2 Test Point Miniature Red TH Red Miniature Testpoint 5000 TP3 TP4 TP5 TP14 4 Test Lead clips and hooks SMT Test Point Body 3 25x1 65mm S1751 46 TP6 TP7 TP8 3 Test Point Miniature Yellow TH Yellow Miniature Testpoint 5004 U1 1 Power Management IC PMIC With 4 Phase 14 A Buck for Processors RVJ0056A VQFN 56 RVJ0056A TPS65941 Q1 U2 1 AEC Q100 Quad Com...

Страница 30: ... MUS 6 Y2 1 Crystal 25 MHz 8pF SMD 3 2x0 75x2 5mm NX3225GA 25 000M STD CRG 2 C1 C94 0 22 µF CAP CERM 22 µF 6 3 V 10 X7R AEC Q200 Grade 1 1206 1206 CGA5L1X7R0J226M160AC C3 0 47000 µF CAP Electric Double Layer 47000 µF 5 5 V 80 20 TH Horizontal D11 5x5mm DX 5R5H473U C16 C17 0 CAP CER 6PF 50V C0G 0402 0402 GCM1555C1H6R0CA16 C79 0 680 µF CAP TA 680 µF 6 3 V 10 0 023 Ω AEC Q200 Grade 1 SMD 7343 40 T510...

Страница 31: ...1 L SV J42 J43 J44 J47 0 Header 100mil 2x1 Tin SMD SMD 2 Leads Body 200x100mil TSM 102 01 T SV P TR R2 R4 R6 0 0 RES 0 5 0 063 W AEC Q200 Grade 0 0402 0402 RK73Z1ETTP R25 0 0 002 RES 0 002 2 1 W 0508 0508 KRL2012E M R002 G T5 TP9 TP10 TP11 TP12 TP13 0 Test Point Miniature Yellow TH Yellow Miniature Testpoint 5004 www ti com Schematic Layout and Bill of Materials SLVUBT0A JUNE 2020 REVISED JANUARY ...

Страница 32: ...1C106K125AC C45 C46 C48 C49 C50 C51 C52 C53 C56 C57 10 Chip Multilayer Ceramic Capacitors for Automotive 1206 3216 Metric GCM31CD70G476ME C54 C55 C59 C60 C61 C62 C63 C64 C65 C66 10 10 µF CAP CERM 10 µF 4 V 20 1 6x 0 8 mm 1 6 0 8 mm NFM18HC106D0G3 C67 C68 C70 C71 C72 C73 C74 C75 C76 C77 C84 11 3 Terminals Chip Multilayer Ceramic Capacitor EMIFIL 0402 NFM15HC105D0G3 C80 C101 C102 C103 C104 C105 6 33...

Страница 33: ... SMD TDK Inductor TFM322512ALMAR47MTAA LBL1 1 PCB Label 0 650 0 200 inch THT 14 423 10 R1 R3 R5 R7 R19 R36 R40 R56 R57 R58 R65 R67 R83 R84 R85 R86 R87 R88 R89 R90 R91 R92 22 0 RES 0 5 0 063 W AEC Q200 Grade 0 0402 0402 RK73Z1ETTP R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R27 R28 R29 R31 R33 R34 R37 R38 R42 R44 R46 R47 R49 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R93 R94 R95 40 10 k RES ...

Страница 34: ...0 TP3 TP4 TP5 TP14 4 Test Lead clips and hooks SMT Test Point Body 3 25 1 65 mm S1751 46 TP6 TP7 TP8 3 Test Point Miniature Yellow TH Yellow Miniature Testpoint 5004 U1 1 Power Management IC PMIC With 4 Phase 14 A Buck for Processors RVJ0056A VQFN 56 RVJ0056A TPS65941 Q1 U2 1 AEC Q100 Quad Comparator PW0014A TSSOP 14 PW0014A LM2901AVQPWRQ1 U3 1 MSP432E401YTPDT PDT0128A TQFP 128 PDT0128A MSP432E401...

Страница 35: ...200 Grade 1 1206 1206 CGA5L1X7R0J226M160AC C3 0 47000 µF CAP Electric Double Layer 47000 µF 5 5 V 80 20 TH Horizontal D11 5 5 mm DX 5R5H473U C16 C17 0 CAP CER 6PF 50 V C0G 0402 0402 GCM1555C1H6R0CA16 C79 0 680 µF CAP TA 680 µF 6 3 V 10 0 023 Ω AEC Q200 Grade 1 SMD 7343 40 T510X687K006AGA023 D1 0 10V Diode Zener 10 V 300 mW SOD 323 SOD 323 MM3Z10VST1G D2 0 40V Diode Schottky 40 V 2 A SOD 123F SOD 1...

Страница 36: ... 01 T SV P TR Q1 0 30 V MOSFET N CH 30 V 27 2 A AEC Q101 SO 8FL SO 8FL NVMFS4C05NT1G R2 R4 R6 R26 R35 R39 0 0 RES 0 5 0 063 W AEC Q200 Grade 0 0402 0402 RK73Z1ETTP R20 R21 0 240 RES 240 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW0402240RJNED R22 0 1 2 k RES 1 2 k 5 0 063 W AEC Q200 Grade 0 0402 0402 CRCW04021K20JNED TP9 TP10 TP11 TP12 TP13 0 Test Point Miniature Yellow TH Yellow Miniature Testpoint ...

Страница 37: ...pdated the EVM Descriptions table in the Introduction 3 Updated the Getting Started section 3 Updated the EVM Details section 5 Changed VSYS_IN to VSYS in the Terminal Blocks section 6 Updated the Configuration Headers section 7 Updated the LDO Headers figure 9 Updated the Stack Up Headers section 10 Updated the Connectors section 13 Updated the EVM Control GPIO and Additional Regulators section 1...

Страница 38: ...other than TI b the nonconformity resulted from User s design specifications or instructions for such EVMs or improper system design or c User has not paid on time Testing and other quality control techniques are used to the extent TI deems necessary TI does not test all parameters of each EVM User s claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects...

Страница 39: ... These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation...

Страница 40: ...y for convenience and should be verified by User 1 Use EVMs in a shielded room or any other test facility as defined in the notification 173 issued by Ministry of Internal Affairs and Communications on March 28 2006 based on Sub section 1 1 of Article 6 of the Ministry s Rule for Enforcement of Radio Law of Japan 2 Use EVMs only after User obtains the license of Test Radio Station as provided in R...

Страница 41: ... any interfaces electronic and or mechanical between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees affiliates contractors or designees 4 4 User assumes all...

Страница 42: ...OR DAMAGES ARE CLAIMED THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT 9 Return Policy Except as otherwise provided TI does not offer any refunds returns or exchanges Furthermore no return of EVM s will be accepted if the package has been opened and no return of the EVM s will be accepted if they are damaged or otherwise not in a resalable condition If User feels it has...

Страница 43: ...s are subject to change without notice TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource Other reproduction and display of these resources is prohibited No license is granted to any other TI intellectual property right or to any third party intellectual property right TI disclaims responsibility for and you wi...

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