SLUU131A – September 2002 – Revised February 2003
8
TPS40001 Based Converter Delivers 10-A Output
4.7
Compensation Design
The TPS40000 uses voltage mode control in conjunction with a high frequency error amplifier. The power circuit
L-C double pole corner frequency f
C
is located in equation (7).
Freq
LC
+
1
2
p
L
OUT
C
OUT
Ǹ
+
5.1 kHz
The output capacitor ESR zero is calculated by equation (8),
F
Z(esr)
+
1
2
p
R
ESR
C
OUT
+
33.8 kHz
where the two POSCAPs ESR of 5 m
Ω
is used in the calculation because the 1
µ
F is effectively out of the picture
at these relatively low frequencies.
The feedback compensation network is implemented to provide two zeroes and three poles. The first pole is
placed near the origin to improve dc regulation.
The first zero is placed below f
C
at 2.2 kHz in equation (9).
f
z1
+
1
2
p
ǒ
R
6
)
R
7
Ǔ
C
15
The second zero is placed at 18 kHz shown in equation (10).
f
z2
+
1
2
p
R
4
C
7
The first pole is placed near the ESR zero frequency in equation (11),
f
p1
+
1
2
p
R
7
C
15
and the second pole is placed at one-half the switching frequency at 150 kHz to allow a high-speed transient
response, shown in equation (12).
f
p2
+
1
2
p
R
4
ǒ
C
7
C
11
C
7
)
C
11
Ǔ
(7)
(8)
(9)
(10)
(11)
(12)
